Advantech PCA-6166, Руководство пользователя

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Chapter 3 Award BIOS Setup 41
3.5.3 SDRAM CAS Latency Time
This controls the latency between SDRAM read command and the
time that the data actually becomes available. Leave this on the
default setting.
3.5.4 DRAM Opt RAS Precharge
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refreshes. If insufficient time is
allowed, leave the default setting on. Refresh may be incomplete and
the DRAM may fail to retain data.
3.5.5 ISA Bus Clock Frequency
This can set the speed of AT bus at one-third or one-fourth of the CPU
clock speed. The default setting is at 7.159 MHz.
3.5.6 Starting point of paging
This value controls the the timing which memory paging operations
start.
3.5.7 PCI Peer Concurrency
This means that more than one PCI device can be active at a time. The
default setting is enabled.
3.5.8 Read Prefetch Memory RD
When this item is enabled, the system can prefetch the next read
instruction and the next process.
3.5.9 Assert TRDY After Prefet
When you select 1QWs, SiS530 asserts its first TRDYnumber for one
transaction after it prefetched one quadword of data from system
memory, otherwise SiS530 asserts its first TRDY number after two
quadwords are prefetched.