ADLINK Technology NuDAQ ACL-8454, Руководство пользователя

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Registers Format
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3.2 Timer/Counter Registers
The 8254 occupies 4 I/O address locations in the ACL-8454 as
shown blow. Users can refer to NEC's or Intel's data sheet for a full
description of the 8254 features, condensed information is specified
in Appendix C. Note that only one of the four 8454 chips can be
enable in the same time.
Address : BASE + 0 ~ BASE + 3
Attribute :
read / write
Data Format :
Base + 0 Counter 0 Register ( R/W)
Base + 1 Counter 1 Register ( R/W)
Base + 2 Counter 2 Register ( R/W)
Base + 3 8254 Mode Control Register (W)
8254 Read Back R egister (R)
3.3 Chip Select Register
There are four 8254 chips on board. However, only one 8254 can be
selected at a moment. The bit 0,1 of the chip select register (CS1
and CS0) are used to select 8254 chip. Whenever a chip is selected
(active), the 8254 I/O address (BASE+0 ~ BASE+3) is selected by this
chip. The active chip is enabled by CS0 and CS1 according the
following table.
Address : BASE + 4
Attribute :
write only
Data Format :
Bit 7 6 5 4 3 2 1 0
Base + 4 -- -- -- -- -- -- CS1 CS0
8254 Chip # CS1 CS0
Chip #1
0 0
Chip #2
0 1
Chip #3
1 0