ADLINK Technology NuDAQ ACL-8454, Руководство пользователя

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Applications
It is really a large number. Share the divider value to the two
counters, for example, the divider of the first stage can be
60000 and the divider of the second stage is 6000.
∵
360,000,000 = 60000 x 6000
Therefore, ‘user configurable cascaded counters’ can be
used to solve this problem. The counter #1 and #2 are
used in this example.
step 3: Set jumper ‘CK1’. The clock source is internal ‘CLOCK2’
and CLOCK2 is defaultly set as 100 K Hz. Then set jumper
‘CK2’ and the clock source is coming for the output of the
‘Last channel (#1)‘.
step 4: Skip these steps.
step 5: Write and verify the control program for counter #1.
step 6: Skip these steps.
step 7: The gate source of the two counter is enable always. Note
the jumper ‘G1’ and ‘G2’ should be removed and no
external gate signals are used.
step 8: Connect the counter #2 output to external device. The
following block diagram illustrates the application
step 9: Write and verify the control program. Please refer the
‘DEMO2.C’ source code.
100 K Hz
COUT1
Counter #1
8254 Chip #1
C
G
O
'H'
Jumper
CK1
Jumper
CLOCK2
COUT2
Counter #2
8254 Chip #1
C
G
O
'H'
Jumper
CK2
Figure 4.2.2 Example of frequency generator (2)