SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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The RBR holds from 5 to 8 bits of data, as specified by the
character size programmed in the Line Control Register (LCR bits
0 & 1). If less than 8 bits are transmitted, then data is right-
justified to the LSB. If parity is used, then LCR bit 3 (parity
enable) and LCR bit 4 (type of parity) are required. Status for the
receiver is provided via the Line-Status Register (LSR). When a
full character is received (including parity and stop bits), the data-
received indication bit (bit 0) of the LSR is set to 1. The host
CPU then reads the Receiver Buffer Register, which resets LSR
bit 0 low. If the character is not read prior to a new character
transfer between the receiver shift register and the receiver buffer
register, the overrun-error status indication is set in LSR bit 1. If
there is a parity error, the error is indicated in LSR bit 2. If a stop
bit is not detected, a framing error indication is set in bit 3 of the
LSR.
Serial asynchronous data is input to the receiver shift register
via the receive data line (RxD). From the idle state, this line is
monitored for a high-to-low transition (start bit). When the start
bit is detected, a counter is reset and counts the 16x clock to 7-
1/2 (which is the center of the start bit). The start bit is judged
valid if RxD is still low at this point. This is known as false start-
bit detection. By verifying the start bit in this manner, it helps to
prevent the receiver from assembling an invalid data character
due to a low-going noise spike on RxD. If the data on RxD is a
symmetrical square wave, the center of the data cells will occur
within 3.125% of the actual center (providing an error margin of
46.875%). Thus, the start bit can begin as much as one 16x
clock cycle prior to being detected.
THR - Transmitter Holding Register, Ports A-H (WRITE Only)
The Transmitter Holding Register (THR) is a serial output
data register that shifts the data to the transmit data line (TxD).
However, the THR data will not pass to the TxD line unless the
tranceiver is first enabled.
The transceiver must be enabled to
transmit data by setting bit-1 of the MCR (Modem Control
Register) to a logic
“1”.
The Transmitter Holding Register (THR) is a serial port output
data register that holds from 5 to 8 bits of data, as specified by
the character size programmed in the Line Control Register. If
less than 8 bits are transmitted, then data is entered right-justified
to the LSB. This data is framed as required, then shifted to the
transmit data line (TxD). In the idle state, TxD is held high. In
Loopback Mode, this data is looped back into the Receiver Buffer
Register.
The status of the THR is provided in the Line Status Register
(LSR). Writing to the THR transfers the contents of the data bus
(D7-D0) to the THR, provided that at least one FIFO location is
available. The THR empty flag in the LSR register will be set to a
logic 1 when at least one FIFO location is available.
DLL & DLM - Divisor Latch Registers, Ports A-H (R/W)
The Divisor Latch Registers form the divisor used by the
internal baud-rate generator to divide the 14.7456MHz clock to
produce an internal sampling clock suitable for synchronization to
the desired baud rate. The output of the baud generator (RCLK)
is sixteen times the baud rate. Two 8-bit divisor latch registers
per port are used to store the divisors in 16-bit binary format. The
DLL register stores the low-order byte of the divisor, DLM stores
the high-order byte.
These registers must be loaded during
initialization.
Note that bit 7 of the LCR register must first be set high to
access the divisor latch registers (DLL & DLM).
Upon loading either latch, a 16-bit baud counter is
immediately loaded (this prevents long counts on initial load).
The clock may be divided by any divisor from 1 to 2
(16-1)
. The
relationship between the baud rate, the divisor, and the
14.7456MHz clock can be summarized in the following equations:
Divisor = 14.7456MHz
16
Baud Rate
MCRDIV
Baud Rate = 14.7456MHz
16
Divisor
MCRDIV
The MCRDIV term represents the state of bit-7 of the MCR
(Mode Control Register) as follows:
MCRDIV = 1 If MCR bit-7=0
MCRDIV = 4 If MCR bit-7=1
The following table shows the correct divisor to use for
generation of some standard baud rates (based on the
14.7456MHz clock). A different external crystal can replace the
14.7456MHz crystal on the circuit board to obtain unique clock
rates. You may contact Acromag Applications Engineering to
explore options in this area.
Table 3.2: Baud Rate Divisors (
14.7456MHz Clock)
BAUD RATE
DIVISOR (N)
MCR
Bit-7=1
MCR
Bit-7=0
Decimal
DLM
(HEX)
DLL
(HEX)
50
200
4608
12
00
300
1200
768
03
00
600
2400
384
01
80
1200
4800
192
00
C0
2400
9600
96
00
60
3600
14,400
64
00
40
4800
19,200
48
00
30
7200
28,800
32
00
20
9600
38,400
24
00
18
19,200
76,800
12
00
0C
28,800
115,200
8
00
08
38,400
153,600
6
00
06
57,600
230,400
4
00
04
230,400
921,600
1
00
01
With respect to this device, the baud rate may be considered
equal to the number of bits transmitted per second (bps). The bit
rate (bps), or baud rate, defines the bit time. This is the length of
time a bit will be held on before the next bit is transmitted. A
receiver and transmitter must be communicating at the same bit
rate, or data will be garbled. A receiver is alerted to an incoming
character by the start bit, which marks the beginning of the
character. It then times the incoming signal, sampling each bit as
near to the center of the bit time as possible.
To better understand the asynchronous timing used by this
device, note that the receive data line (RxD) is monitored for a
high-to-low transition (start bit). When the start bit is detected, a
counter is reset and counts the 16x sampling clock to 7-1/2 (the
center of the start bit). The receiver then counts from 0 to 15 to
sample the next bit near its center, and so on, until a stop bit is
detected, signaling the end of the data stream. Use of a
sampling rate 16x the baud rate reduces the synchronization
error that builds up in estimating the center of each successive bit
