SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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P2 pin assignments are unique to each IOS model (see
Table 2.1) and normally correspond to the pin numbers of the
field I/O interface connector on the carrier board (you should
verify this for your carrier board).
Table 2.1: IOS-521 Field I/O Pin Connections (P2)
Pin Description
Number
Pin Description
Number
COMMON
1
COMMON
26
TXD-_A
2
TXD-_F
27
TXD+_A
3
TXD+_F
28
RXD-_A
4
RXD-_F
29
RXD+_A
5
RXD+_F
30
COMMON
6
COMMON
31
TXD-_B
7
TXD-_G
32
TXD+_B
8
TXD+_G
33
RXD-_B
9
RXD-_G
34
RXD+_B
10
RXD+_G
35
COMMON
11
COMMON
36
TXD-_C
12
TXD-_H
37
TXD+_C
13
TXD+_H
38
RXD-_C
14
RXD-_H
39
RXD+_C
15
RXD+_H
40
COMMON
16
COMMON
41
TXD-_D
17
No Connection
42
TXD+_D
18
No Connection
43
RXD-_D
19
No Connection
44
RXD+_D
20
No Connection
45
COMMON
21
No Connection
46
TXD-_E
22
No Connection
47
TXD+_E
23
No Connection
48
RXD-_E
24
No Connection
49
RXD+_E
25
No Connection
50
In Table 2.1, a suffix of “_A”, “_B”, “_C”, to “_H” is appended
to each pin label to denote its port association. A brief
description of each of the serial port signals at P2 is included
below. A complete functional description of all P2 pin functions is
included in Section 4.0 (Theory Of Operation).
P2 Pin Signal Descriptions
SIGNAL
DESCRIPTION
RxD_A
to
RxD_H
Receive Data Line Input - This is the receive data
input line. During Loopback Mode, the RxD input is
disabled from the external connection and
connected to the TxD output internally.
TxD_A
to
TxD_H
Transmit Data Line Output - This is the transmit
output data line. In the idle state, this signal line is
held in the mark (logic 1) state. During Loopback
Mode, the TxD output is internally connected to the
RxD input.
Noise and Grounding Considerations
The serial channels of this module are non-isolated and
share a common signal ground connection. Further, the IOS-521
is non-isolated between the logic and field I/O grounds since
signal common is electrically connected to the IOS module
ground. Consequently, the field interface connections are not
isolated from the carrier board and backplane. Care should be
taken in designing installations without isolation to avoid noise
pickup and ground loops caused by multiple ground connections.
The signal ground connection at the communication ports are
common to the IOS interface ground, which is typically common
to safety (chassis) ground when mounted on a carrier board and
inserted in a backplane. As such, be careful not to attach signal
ground to safety ground via any device connected to these ports,
or a ground loop will be produced, and this may adversely affect
operation.
The communication cabling of the P2 interface carries digital
data at a high transfer rate. For best performance, increased
signal integrity, and safety reasons, you should isolate these
connections away from power and other wiring to avoid noise-
coupling and crosstalk interference. EIA/TIA-422B
communication distances are generally limited to less then 4000
feet. Always keep interface cabling and ground wiring as short as
possible for best performance.
3.0 PROGRAMMING INFORMATION
ADDRESS MAPS
This board is addressable in the I/O Server Module space to
control the interface configuration, data transfer, and steering
logic of eight EIA/TIA-422B serial ports. As such, three types of
information are stored in the I/O space: control, status, and data.
These registers are listed below along with their mnemonics used
throughout this manual.
The I/O space may be as large as 64, 16-bit words (128
bytes) using address lines A1..A6, but the IOS-521 uses 64 lower
byte locations of this space. The I/O space address map for the
IOS-521 is shown in Table 3.1. Note that the base address for
the IOS module I/O space (see your carrier board instructions)
must be added to the addresses shown to properly access the
I/O space. All accesses are performed on an 8-bit word basis
(D0..D7).
SERIAL DATA REGISTERS (Per Serial Port):
RBR
Receiver Buffer Register
THR
Transmitter Holding Register
SERIAL STATUS REGISTERS (Per Serial Port):
LSR
Line Status Register
MSR
Modem Status Register
ISR
Interrupt Status Register
SERIAL CONTROL REGISTERS (Per Serial Port):
LCR
Line Control Register
FCR
FIFO Control Register
MCR
Modem Control Register
DLL
Divisor Latch LSB
DLM
Divisor Latch MSB
IER
Interrupt Enable Register
SCR
Scratch Pad/Interrupt Vector Register
EFR
Enhanced Feature Register
XON-1
XON-1 Low Byte
XON-2
XON-2 High Byte
XOFF-1
XOFF-1 Low Byte
XOFF-2
XOFF-2 High Byte
Shaded registers are accessible only after writing “BF” to the line
Control Register (LCR).
Note that some functions share the same register address.
For these items, the address lines are used along with the LCR
(Line Control Register) and/or the read and write signals to
determine the function required. The DLL and DLM registers are
only accessible when LCR bit-
7 is set to “1”. The EFR, Xon 1,2,
and Xoff 1,2 locations are accessible only when the LCR is set to
“BF” hex.
