SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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stack it into the data buffer or FIFO and these conditions are
configured via bits 0-3 of the Enhanced Feature Register (EFR).
Programming Example
The following example will demonstrate data transfer
between one channel of the host IOS-521 and another node.
Both nodes will use the FIFO Mode of operation with a FIFO
threshold set at 60 bytes. The data format will use 8-bit
characters, odd-parity, and 1 stop bit.
Please refer to Table 3.1 for addr
ess locations. The “H” following
data below refers to the Hexadecimal format.
1. Write 80H to the Line Control Register (LCR).
This sets the Divisor Latch Access bit to permit access to the
two divisor latch bytes used to set the baud rate. These
bytes share addresses with the Receive and Transmit
buffers, and the Interrupt Enable Register (IER).
2. Write 00H to the Divisor Latch MSB (DLM). Write 60H to the
Divisor Latch LSB (DLL).
This sets the divisor to 96 for 9600 baud (i.e. 9600 =
14.7456MHz [16*96] ).
3. Write 0BH to the Line Control Register (LCR).
This first turns off the Divisor Latch Access bit to cause
accesses to the Receiver and Transmit buffers and the
Interrupt Enable Register. It also sets the word length to 8
bits, the number of stop bits to one, and enables odd-parity.
4. (OPTIONAL) Write xxH to the Scratch Pad Register.
This has no effect on the operation, but is suggested to
illustrate that this register can be used as a 1-byte memory
cell. Optionally, this register is also used to store the
interrupt vector for the port. A read of this register will be
performed in response to an interrupt cycle.
5. Write 07H to the Interrupt Enable Register (IER).
This is the first step to enable the receiver line status
interrupt. Note bit-
3 of the MCR must also be set to logic “1”
to enable interrupts. The line status interrupt is used to
signal error cases, such as parity or overrun errors. The
received data available and transmit holding buffer empty
interrupts have also been enabled to aide control by the host
CPU in moving data back and forth.
6. Write C7H to the FIFO Control Register (FCR).
This enables and initializes the transmit and receive FIFO‟s,
and sets the trigger level of the receive FIFO interrupt to 60
bytes.
7. Read C1H from the Interrupt Status Register (ISR).
This is done to check that the device has been programmed
correctly. The upper nibble “C” indicates that the FIFO‟s
have been enabled and the lower nibble “1” indicates that no
interrupts are pending.
8. Write 0AH to the Modem Control Register (MCR).
This enables interrupts and sets the Ready-To-Send bit and
asserts the RTS* signal line. It is used to enable transmit
data output for the port. Note the modem control lines, either
input or output, have no effect on the parallel-to-serial output
data or serial-to-parallel input data. These lines interact only
through CPU control to provide the handshaking necessary
for this data transfer protocol.
9. The host should begin writing data repeatedly to the
Transmitter Holding Register.
This loads the transmit FIFO and initiates transmission of
serial data on the TxD line. The first serial byte will take
about 100us to transmit, so it is likely that the transmit FIFO
will fill before the first byte has been sent.
10. Read data repeatedly from the Receiver Buffer Register.
After 60 bytes have been received (or fewer bytes with a
timeout), an interrupt will be generated. INTREQ0* will go
active to signal the host CPU that it can begin reading the
receive FIFO.
11 The host should acknowledge the interrupt
To acknowledge and clear it, an interrupt select cycle should
be executed. Then begin reading the receive FIFO data.
