Acromag IOS-521 Series, Руководство пользователя

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SERIES IOS-521 I/O SERVER MODULE EIA/TIA-422B SERIAL COMMUNICATION MODULE
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EFR Bit FUNCTION PROGRAMMING
6 RTS
1
Hardware
Flow
Control
0 = Disable Automatic RTS flow
control.
1= Enable Automatic RTS flow
control. The RTS pin can be
automatically controlled to
indicate local buffer overflows to
remote buffers. When automatic
hardware flow control is enabled,
an interrupt will be generated
when the receive FIFO is filled to
the program trigger level and
RTS will go to a logic “1” at the
next trigger level. RTS will return
to a logic “0” when data is
unloaded below the next lower
trigger level. RTS functions
normally when hardware flow
control is disabled. FCTR bits0-1
are used to set the RTS delay
timer/trigger level.
7 CTS
2
Hardware
Flow
Control
0 = Disable Automatic CTS flow
control.
1 = Enable Automatic CTS flow
control.
Notes :
1. For this model RTS is used to enable its corresponding
transmitter for output of the TxD signal. The RTS signals do
not have transmitter output paths on this model.
2. The CTS signals do not have a receiver input path on this
model.
A power-up or system reset sets all EFR bits to 0.
XON/XOFF-1,2 Registers, Ports A-H (R/W)
These registers hold the programmed XON and XOFF
characters for software flow control. XON or XOFF characters
may be 1 or 2 bytes long. The UART compares incoming data to
these values and restarts (XON) or suspends (XOFF) data
transmission when a match is detected. Note that access to
these registers is granted only after writing “BF” to the Line
Control Register (LCR). All XON/XOFF bits are set to 0 upon
power-up or system reset.
Identification Space (Read Only, 32 even-byte addresses)
Each IOS module contains identification (ID) information that
resides in the ID space per the IOS module specification. This
area of memory contains 32 bytes of information at most. Both
fixed and variable information may be present within the ID
space. Fixed information includes the "IOS" identifier, model
number, and manufacturer's identification codes. Variable
information includes unique information required for the module.
The IOS-521 ID Space does not contain any variable (e.g. unique
calibration) information. ID Space bytes are addressed using
only the even addresses in a 64 byte block on the “Little Endian”
PCI buses.
The IOS-521 ID Space contents are shown in Table 3.3.
Note that the base-address for the IOS module ID space (see
your carrier board instructions) must be added to the addresses
shown to properly access the ID information. Execution of an ID
Space Read operation requires 0 wait states.
Table 3.3: IOS-521 ID Space Identification (ID)
Hex Offset
From ID
Base
Address
Numeric
Value
(Hex) Field Description
00 49
02 50
04 41
06 43
08 A3 Acromag ID Code
0A 25 IOS Model Code
1
0C 00 Not Used
(Revision)
0E 00 Reserved
10 00 Not Used
12 00 Not Used
14 0C Total Number of
ID PROM Bytes
16 11 CRC
18 to 3E yy Not Used
Notes (Table 3.3):
1. The IOS model number is represented by a two-digit code
within the ID space (the IOS-521 model is represented by 25
Hex).
THE EFFECT OF RESET
A software or hardware reset puts the serial channels into an
idle-mode until initialization (programming). A reset initializes the
receiver and transmitter clock counters. It also clears the Line-
Status Register (LSR), except for the transmitter shift-register
empty (TEMT) and transmit holding-register empty (THRE) bits
which are set to 1 (note that when interrupts are subsequently
enabled, an interrupt will occur due to THRE being set). The
Modem Control Register (MCR) is also cleared. All of the
discrete signal lines, memory elements, and miscellaneous logic
associated with these register bits are cleared, de-asserted, or
turned off. However, the Line Control Register (LCR), divisor
latches, Receiver Buffer Register (RBR), and Transmitter Holding
Register (THR) are not affected. The following table summarizes
the effect of a reset on the various registers and internal and
external signals:
REG/SIGNAL RESET CTRL STATE/EFFECT
REGISTERS:
IER Reset All Bits low
ISR Reset Bit 0 high, Bits 1-7 low
LCR Reset All bits low
MCR Reset All bits low
FCR Reset All bits low
LSR Reset All bits low, except bits 5 & 6
are high
MSR Reset Bits 0-3 low, bit 4
corresponds to input signal
EFR Reset All bits low
XON-1,2 Reset All bits low
XOFF-1,2 Reset All bits low
TRG Reset All bits low