
AXM-VFX-EDK User’s Manual Mezzanine Board
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
11
EDK Input/Output Registers (Read/Write) –
(P 8004H)
The AXM-VFX-EDK LVTTL channels may be individually accessed via
this register at the carrier P 8004H. This includes all 30 general
purpose LVTTL channels on the AXM-VFX-EDK. Each channel is
controlled by its corresponding data bit, as shown in the register mapping
table below. Channel input signal levels are determined by reading this
register. Likewise, channel output signal levels are set by writing to this
register. Note that the data direction, input or output, must first be set via
the Differential Direction register at PCIBAR2 plus 8008H.
D31 D30 D29 D28 D27 D26 D25
Not Used
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
D23 D22 D21 D20 D19 D18 D17
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
D15 D14 D13 D12 D11 D10 D9
I/O 15
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 9
D7 D6 D5 D4 D3 D2 D1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
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Channel read/write operations use 8-bit, 16-bit, or 32-bit data transfers
with the lower ordered bits corresponding to the lower-numbered channels
for the register of interest. All input/output channels are configured as inputs
following a power-on or software reset. Data-bits 30 and 31 are not used
and will return 0 when read. Data bits 0 through 7 in the AXM-D03 module
will read back the last data values written to those bits.
DIFFERENTIAL
INPUT/OUTPUT
REGISTERS