AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 35 -
http://www.acromag.com
- 35 -
www.acromag.com
6
100000
CTS# or RTS# change of state
X
000001
None (default)
Note that ISR bit 0 can be used to indicate whether an interrupt is pending
(bit 0 low when interrupt is pending).
Bits 6 and 7 are set when bit 0 of the FIFO Control Register is set to 1. A
power-up or system reset sets ISR bit 0 to
logic “1”, and bits 1 to 7 to logic
“0”.
3.4.6 FIFO Control Register (FCR)
–
Write Only
This write-only register is used to enable and clear the FIFO buffers, set the
transmit/receive FIFO trigger levels, and select the type of DMA signaling.
Table 3.13 FIFO Control Register
FCR BIT FUNCTION
0
Tx and Rx FIFO Enable:
0 = disable the transmit and receive FIFO (default).
1 = enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits are written
or they will not be programmed.
1
Rx FIFO Reset:
0 = no receive FIFO reset (default).
1 = Reset the receive FIFO pointers and FIFO level counter
logic (the receive shift register is not cleared or altered). This
bit will return to logic 0 after resetting the FIFO.
2
Tx FIFO Reset:
0 = No transmit FIFO reset (default).
1 = Reset the transmit FIFO pointers and FIFO level counter
logic (the transmit shift register is not cleared or altered). This
bit will return to logic 0 after resetting the FIFO.
3
DMA Mode Select:
0 = Set DMA mode to 0 (default).
1 = Set DMA mode to 1.
This bit has no effect and is provided for legacy software
compatibility.
5,4
1
Transmit FIFO Trigger Select:
