AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 25 -
http://www.acromag.com
- 25 -
www.acromag.com
REGB[18]
Global Interrupt Disable:
0 = Global interrupt enabled. Interrupts to PCIe host
are enabled (default).
1 = Global interrupt disabled. Interrupts to PCIe host
are disabled.
REGB[17]
Wake-up Interrupt Disable:
0 = Wake-up interrupt is generated when UART exits
sleep mode (default).
1 = No wake-up interrupt is generated when UART
exits sleep mode.
REGB[16]
Enable Simultaneous Configuration:
0 = write to each UART configuration registers
individually (default).
1 = Enable simultaneous write to all 4 UART
configuration registers.
3.2.10 MPIO Registers
The MPIO pins of the Exar device are reserved for device identification. As
inputs, MPIO[15:0] on the AP513 module will read 0x0009 through the
MPIOLVL registers.
3.3 Transmit and Receive Data
There are two methods to load transmit data and unload receive data from
each UART channel. First, there is a transmit data register and receive data
register for each UART channel as shown in Table 3.2 set to ease
programming. These registers support 8, 16,
24 and 32-bit wide format. In
the 32-bit format, it increases the data transfer rate on the PCI bus.
Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the
Line Status Register (LSR) content in the UART channel register is paired
along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately.
Furthermore, the XR17V354 supports 32-bit read/write operation of up to
256 bytes of data.
The second method is through each UART channel’s transmit holding
register (THR) and receive holding register (RHR). The THR and RHR registers
are 16550 compatible so their access is limited to 8-bit format. The software
driver must separately read the LSR content for the associated error flags
before reading the data byte.
