AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 31 -
http://www.acromag.com
- 31 -
www.acromag.com
3.4.4 Interrupt Enable Register (IER)
–
Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data
ready, transmit empty, line status and modem status registers. These
interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
3.4.4.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit [0] = logic 1) and receive interrupts (IER bit
[0] = logic 1) are enabled, the RHR interrupts (see ISR bits [4:3]) status will
reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level
is reached. Both the ISR register status bit and the interrupt will be cleared
when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is
transferred from the shift register to the receive FIFO. It is reset when the
FIFO is empty.
3.4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0]
enables the XR17V354 in the FIFO polled mode of operation. Since the
receiver and transmitter have separate bits in the LSR either can be used in
the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO
mode).
B. LSR BIT-1 indicates an overrun error has occurred and that data in the
FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the
data byte in RHR, if any.
D. LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is
empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO
Table 3.11 Interrupt Enable
Register
IER BIT
INTERRUPT ACTION
0
RX Interrupt Enable:
0 = Disable receive data ready interrupt (default).
