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AP513 ACROPACK

USER

’S MANUAL

Acromag, Inc. Tel: 248-295-0310

- 17 -

http://www.acromag.com

- 17 -

www.acromag.com

determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.

Table 3.1 PCI Configuration
Registers

Address

Offset

D31 D24 D23 D16 D15 D8 D7 D0

0x00

Device ID

0x0354

Vendor ID

0x13A8

0x04

Status

Command

0x08

Class Code=0x070002

Rev ID=

Current REV

0x0C

BIST

Header

Latency

Cache

0x10

Memory Base Address for Memory Accesses

to PCIe interrupt and I/O registers

16K Space

(BAR0)

0x14-

0x28

Not Used

0x2C

Subsystem ID

0x0000

Subsystem Vendor ID

0x0000

0x30

Not Used

0x34-

0x38

Reserved

0x3C

Max_Lat

Min_Gnt

Inter. Pin

Inter. Line

This board is allocated a 16K byte block of memory (BAR0), to access UART
and device configuration registers. Only 4K is used, as the upper 12K is for
channels 4-7 and a second 'slave' UART' connected to the master that does
not exist on the AP513 module.

3.2 UART and Device Configuration Registers

The Device Configuration Registers and the four individual UART
Configuration Registers occupy 4K of PCI bus memory address space. These
registers are offset from the BAR0 address as identified in the PCIe
Configuration Registers in the previous section.

Each UART Configuration Register occupies 1K byte of memory space that
include the 16550 compatible registers.

The Device Configuration Registers are accessible from all UART channels,
however not all bits can be controlled by all channels. The control of the
8XMODE, 4XMODE, RESET, and SLEEP bits are only available for that
particular channel.

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Содержание AcroPack AP513

Страница 1: ...Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2019 Acromag Inc Printed in the USA Data and specifica...

Страница 2: ...odels 6 Figure 1 1 AP513 Block Diagram 6 1 3 1 Ordering Information 6 Table 1 1 Ordering Options 6 1 3 2 Key Features 6 1 3 3 Key Features PCIe Interface 7 1 4 Signal Interface Products 7 1 5 Software...

Страница 3: ...ion 22 3 2 3 8XMODE 7 0 default 0x00 23 3 2 4 4XMODE 15 8 default 0x00 23 3 2 5 RESET 23 16 default 0x00 23 3 2 6 SLEEP 31 24 default 0x00 24 3 2 7 DVID 15 8 24 3 2 8 DREV 7 0 24 3 2 9 REGB 23 16 defa...

Страница 4: ...3 4 9 Line Status Register LSR Read Only 39 Table 3 17 Line Status Register 40 3 4 10 Modem Status Register MSR Read Only 41 Table 3 18 Modem Status Register 41 3 4 11 Modem Status Register MSR Write...

Страница 5: ...iderations 50 5 3 1 Operating Temperature 50 5 3 2 Other Environmental Requirements 51 5 3 2 1 Relative Humidity 51 5 3 2 2 Isolation 51 5 3 3 Vibration and Shock Standards 51 5 3 4 EMC Directives 51...

Страница 6: ...p current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyright...

Страница 7: ...olation from the other 3 ports Figure 1 1 AP513 Block Diagram 1 3 1 Ordering Information The AcroPack ordering options are given in the following table Table 1 1 Ordering Options Model Number Type of...

Страница 8: ...bit timer counter uses an internal 125MHz clock as the clock source and can be set to be a single shot or re triggerable and can generate an interrupt 1 3 3 Key Features PCIe Interface PCIe Bus The AP...

Страница 9: ...ct sold separately consisting of VxWorks software This software Model APSW API VXW is composed of VxWorks real time operating system libraries for all AcroPack modules VPX I O board products and PCIe...

Страница 10: ...c or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unp...

Страница 11: ...In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature 2 3 Board Configuration Power should be removed from...

Страница 12: ...ated GND_A 1 RSVD ISOL 4 RSVD ISOL 3 RSVD ISOL 6 Field I O 3 3 2 2 RXD_A 5 RSVD ISOL 8 RSVD ISOL 7 RSVD ISOL 10 Field I O 5 5 3 3 TXD_A 9 RSVD ISOL 12 RSVD ISOL 11 RSVD ISOL 14 Field I O 7 7 4 4 CTS_A...

Страница 13: ...D ISOL 37 RSVD ISOL 40 RSVD ISOL 39 RSVD ISOL 42 RSVD ISOL 41 RSVD ISOL 44 RSVD ISOL 43 RSVD ISOL 46 RSVD ISOL 45 RSVD ISOL 48 RSVD ISOL 47 RSVD ISOL 50 RSVD ISOL 49 Field I O 26 26 38 47 Isolated GND...

Страница 14: ...ISOL 72 RSVD ISOL 71 RSVD ISOL 74 Field I O 37 37 19 19 RXD_D 73 RSVD ISOL 76 RSVD ISOL 75 RSVD ISOL 78 Field I O 39 39 20 20 TXD_D 77 RSVD ISOL 80 RSVD ISOL 79 RSVD ISOL 82 Field I O 41 41 21 21 CTS_...

Страница 15: ...Electromechanical Specification REV 1 2 with exceptions shown in Table 2 2 and noted below Threaded metric M2 5 screws and spacers are supplied with the AP carriers to provide additional stability fo...

Страница 16: ...pins that are reserved in the mini PCIe specification Use of fuses on these power supplies along with new Present signal on pin 45 to allow support of mini PCIe cards from other vendors that cannot t...

Страница 17: ...isters When the computer is first powered up the computer s system configuration software scans the PCIe bus to determine what PCIe devices are present The software also determines the configuration r...

Страница 18: ...his board is allocated a 16K byte block of memory BAR0 to access UART and device configuration registers Only 4K is used as the upper 12K is for channels 4 7 and a second slave UART connected to the m...

Страница 19: ...ad only Interrupt 0x00 0x0081 INT1 15 8 Read only 0x00 0x0082 INT2 23 16 Read only 0x00 0x0083 INT3 31 24 Read only 0x00 0x0084 TIMERCNTL Read Write Timer Control 0x00 0x0085 REGA Reserved 0x00 0x0086...

Страница 20: ...h a 32 bit wide register INT3 INT2 INT1 and INT0 The first scheme uses INT0 bits 7 0 along with the Interrupt Status Register ISR of the individual UART channels Each bit gives an indication of the ch...

Страница 21: ...cted or special char detected 5 1 0 1 Reserved 6 1 1 0 MPIO pin s Reported in channel 0 only 7 1 1 1 Timer Counter Reported in channel 0 only 3 2 1 1 Interrupt Clearing Wake up Indicator is cleared by...

Страница 22: ...er output frequency Timer input clock 16 bit Timer value The least significant bit of the timer is being bit 0 of the TIMERLSB with most significant bit being bit 7 in TIMERMSB Notice that these regis...

Страница 23: ...l it times out reaches the terminal count of N clocks at which time it will become LOW and stay LOW If the Timer is re started before the Timer times out the counter is reset and the Timer will wait f...

Страница 24: ...other bits are read only in channel 0 Logic 0 default selects normal 16X sampling with 4XMODE 0x00 and logic one selects 8X sampling rate Transmit and receive data rates will double by selecting 8X I...

Страница 25: ...at any of the 4 UART channels A receive data start bit transition HIGH to LOW in normal mode A data byte is loaded into the transmitter A change of logic state on any of the modem inputs so that any...

Страница 26: ...receive data from each UART channel First there is a transmit data register and receive data register for each UART channel as shown in Table 3 2 set to ease programming These registers support 8 16 2...

Страница 27: ...ons 0x0100 0x0500 0x0900 and 0x0D00 The RX FIFO data can be read out 32 bits at a time at memory locations 0x0100 channel 0 0x0500 channel 1 0x0900 channel 2 and 0x0D00 channel 3 This operation is 4 t...

Страница 28: ...egister THR Transmit Holding Register Read only Write only LCR 7 0 0 0 0 0 DLL Divisor LSB Read Write LCR 7 1 0 0 0 1 IER Interrupt Enable Register Read Write LCR 7 0 0 0 0 1 DLM Divisor MSB Read Writ...

Страница 29: ...el This time out delay is 4 word lengths as defined by LCR bits 1 0 plus 12 bits time The RHR interrupt is enabled by IER bit 0 3 4 2 Transmitter The transmitter section comprises of a 256 byte FIFO a...

Страница 30: ...iver The rate is programmed through registers DLM DLL and DLD which are only accessible when LCR bit 7 is set to logic 1 The BRG divisor DLL DLM and DLD registers defaults to 1 DLL 0x01 DLM 0x00 DLD 0...

Страница 31: ...al Data Rates with Internal 125MHz Clock at 16X Sampling Required Output Data Rate Divisor for 16X Clock decimal Divisor Obtainable in XR17V354 DLM Program Value HEX DLL Program Value HEX DLD Program...

Страница 32: ...be cleared when the FIFO drops below the trigger level C The receive data ready bit LSR bit 0 is set as soon as a character is transferred from the shift register to the receive FIFO It is reset when...

Страница 33: ...n the TX FIFO fall below the programmed trigger level and again when the TX FIFO is empty 2 Receive Line Status Interrupt Enable 0 Disable the receiver line status interrupt default 1 Enable the recei...

Страница 34: ...set to 1 3 4 5 Interrupt Status Register ISR Read Only The Interrupt Status Register is used to indicate that a prioritized interrupt is pending and the type of interrupt that is pending Six levels of...

Страница 35: ...wakes up from the sleep mode 3 4 5 2 Interrupt Clearing LSR interrupt is cleared by a read to the LSR register RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level RXRDY...

Страница 36: ...ster FCR BIT FUNCTION 0 Tx and Rx FIFO Enable 0 disable the transmit and receive FIFO default 1 enable the transmit and receive FIFOs This bit must be set to logic 1 when other FCR bits are written or...

Страница 37: ...will issue a receive interrupt when the number of characters in the FIFO crosses the trigger level Refer to Table 3 10 for selections The FCTR 7 6 are associated with these 2 bits Note that the receiv...

Страница 38: ...this register The individual bits of this register control the format of the data character as follows Table 3 15 Line Control Register LCR Bit FUNCTION PROGRAMMING 1 0 Word Length Select 0 0 5 Data...

Страница 39: ...s indication 3 Wait for the transmitter to become idle when the Transmitter Empty status signal is set high TEMT 1 then clear the break when normal transmission has to be restored 7 Baud Rate Divisors...

Страница 40: ...s mode any RX character received will enable Xon 61 Not Used Must be logic 0 71 Divide by Four 0 Divide by one The internal 125MHz clock is fed directly to the Programmable Baud Rate Generator without...

Страница 41: ...efault 1 Parity Error the received character does not have the correct parity as configured via LCR bits 3 4 This bit is set high on detection of a parity error and reset low when the host CPU reads t...

Страница 42: ...in the FIFO Note that LSR Bits 1 4 are the error conditions that produce a receiver line status interrupt a priority 1 interrupt in the ISR register when any one of these conditions are detected This...

Страница 43: ...ote that not all UART signal paths are used by the AP513 models and their corresponding UART pins are tied high 3 3 This includes RI Ring Indicator DSR Data Set Ready and CD Carrier Detect A power up...

Страница 44: ...iving characters by resetting this bit to a logic 0 The receiver will operate in one of the following ways If the receiver is idle RX pin is HIGH at the time of setting this bit the next character wil...

Страница 45: ...e register has no effect on the operation of either serial channel It is provided as an aide to the programmer to temporarily hold data 3 4 13 Feature Control Register FCTR Read Write This register co...

Страница 46: ...PROGRAMMING 3 0 Software Flow Control 00XX No Transmit Flow Control 10XX Transmit Xon1 Xoff1 01XX Transmit Xon2 Xoff2 11XX Transmit Xon1 and Xon2 Xoff1 and Xoff2 XX00 No receive Flow Control XX10 Rece...

Страница 47: ...local buffer overflows to remote buffers When automatic hardware flow control is enabled an interrupt will be generated when the receive FIFO is filled to the program trigger level and RTS will go to...

Страница 48: ...racters in the receive FIFO The FIFO level byte count register is read only The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO which reduces CP...

Страница 49: ...ll be set to a logic 1 This bit will clear after the read 2 Transmit XOFF Indicator If the last transmitted control character was a Xoff character or characters Xoff1 Xoff2 this bit will be set to a l...

Страница 50: ...e Procedure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the...

Страница 51: ...tion with an AcroPack module will require purchase of the Heatsink AP CC 01 Table 5 1 Power Requirements Summarized below are the expected current draws for each of the specified power supply voltages...

Страница 52: ...00Hz 5G 2 Hours axis Vibration Random Operating Designed to comply with IEC 60068 2 64 10 500Hz 5G rms 2 Hours axis Shock Operating Designed to comply with IEC 60068 2 27 30G 11ms half sine 50G 3mS ha...

Страница 53: ...p www acromag com 52 www acromag com 1 FIT is Failures in 109 hours 5 5 PCIe Bus Specifications Compatibility Conforms to PCI Express Base Specification Revision 2 0 Line Speed Gen1 2 5Gbps Lane Opera...

Страница 54: ...248 295 0310 53 http www acromag com 53 www acromag com Appendix A AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP CC 01...

Страница 55: ...ER S MANUAL Acromag Inc Tel 248 295 0310 54 http www acromag com 54 www acromag com 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secure w...

Страница 56: ...P513 ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 55 http www acromag com 55 www acromag com 4 AP CC 01 Installation is complete Note Make sure the thermal pad is making contact with the UART I...

Страница 57: ...of whose contents are lost when power is removed Yes No Type SRAM SDRAM etc UART Internal Registers FIFOs SRAM Size 4k bytes User Modifiable Yes No Function UART Communication Process to Sanitize Pow...

Страница 58: ...ease Date DD MMM YYYY Version EGR DOC Description of Revision 16 JAN 2019 Prelim ENZ Initial Preliminary Version 15 MAY 2019 A ENZ ARP Initial Release 11 JUL 2019 B ENZ ARP Removed channel 4 7 registe...

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