AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 29 -
http://www.acromag.com
- 29 -
www.acromag.com
3.4.2.3 Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 256 bytes of transmit data.
The THR empty flag (LSR bit [5]) is set whenever the FIFO is empty. The THR
empty flag can generate a transmit empty interrupt (ISR bit [1]) when the
amount of data in the FIFO falls below its programmed trigger level (see
TXTRG register). The transmit empty interrupt is enabled by IER bit [1]. The
TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
3.4.3 Baud Rate Generator Divisors (DLM, DLL and DLD)
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the
transmitter and receiver. The prescaler is controlled by a software bit in the
MCR register. The MCR register bit [7] sets the prescaler to divide the
internal 125 MHz clock by 1 or 4. The output of the prescaler clocks to the
BRG. The BRG further divides this clock by a programmable divisor between
1 and (2
16
- 0.0625) in increments of 0.0625 (1/16) to obtain a 16X, 8X or 4X
sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling.
3.4.3.1 DLM[7:0], DLL[7:0] and DLD[3:0]
The Baud Rate Generator (BRG) generates the data rate for the transmitter
and receiver. The rate is programmed through registers DLM, DLL and DLD
which are only accessible when LCR bit [7] is set to logic 1.
The BRG divisor (DLL, DLM and DLD registers) defaults to 1 (DLL = 0x01, DLM
= 0x00, DLD = 0x00). The DLL and DLM registers provide the integer part of
the divisor and the DLD register provides the fractional part of the divisor.
Only the four lower bits of the DLD are implemented and they are used to
select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111).
Programming the Baud Rate Generator Registers DLL, DLM and DLD
provides the capability for selecting the operating data rate. Table 3.5 shows
the divisor for some standard and non-standard data rates when using the
internal 125 MHz clock at 16X clock rate. If the pre-scaler is used (MCR bit
[7] = 1), the output data rate will be 4 times less than that shown in Table
3.5. At 8X sampling rate, these data rates would double. At 4X sampling
rate, these data rates would quadruple. Also, when using 8X or 4X sampling
mode, note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is
an odd number. For data rates not listed in Table 3.5, the divisor value can
be calculated with the following equation(s):
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler) /
(desired data rate x 16),
WHEN 8XMODE = 0 AND 4XMODE = 0
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler /
(desired data rate x 8),
WHEN 8XMODE = 1 AND 4XMODE = 0
Calculated Divisor (decimal) = (125 MHz clock frequency / prescaler /
(desired data rate x 4),
WHEN 8XMODE = 0 AND 4XMODE = 1
