Acer Altos G610, Руководство пользователя

Страница: 14 / 156

1 System overview 4
Memory
The four DIMM sockets on board accept four 1024-MB registered
SDRAM DIMMs for a maximum memory capacity of 4 GB.
For data integrity, the default setting of the ECC (error correcting code)
function of the memory system in BIOS is enabled. Refer to “IPMI
Configuration” on page 107 for more information on this BIOS
parameter.
Note: The SDRAM module should work under 3.3 volts only;
5-volt memory devices are not supported.
The system board supports both 100 and 133 MHz registered SDRAMs;
66 MHz SDRAMs are not supported.
System chipsets
Server Works LE III north and south bridge
The Server Works LE III north and south bridge chipsets are specifically
designed to meet the needs of high performance systems.
• CNB30LE (champ north bridge) is in charge of the host bus
interfacing and memory bus control. The north bridge provides
one 32-bit PCI bus running at 33 MHz and one 64-bit secondary PCI
bus running at 33/66 MHz.
• OSB4 (open south bridge) subset provides the legacy ISA interface,
USB port, ATA33, and System Management (SM) bus. The BMC
(Baseboard Management Control) board is attached to the
mainboard and connected to the south bridge that supports the
ASM and RDM functions and the industry standard IPMI protocol
as well.
AA G610.book Page 4 Monday, October 22, 2001 9:46 AM