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ACCES I/O Products, Inc. 

MADE IN THE USA 

mPCIe- and M.2-AIO16-16F Family Manual 

 

4

 

Rev B7a

 

C

HAPTER 

7:

 

S

OFTWARE 

I

NTERFACE

 

How to use 

The ADAS3022 is a flexible data acquisition system-on-chip that has numerous features and modes of operation, and additional modes and features are added by our advanced FPGA 
design. 

This flexibility can seem overwhelming, but we’ve designed our

 AIOAIO.dll API to make using this ADC simple for 99% of customer use-cases, based on 30+ years of customer feedback. 

We strongly recommend you ignore the register details provided in Chapter 7: Software Interface and the discussions regarding low-level control of the ADC in the second half of this 
chapter.  Instead, simply refer to the AIOAIO Software Reference (.html) manual [link] and the source code to the variety of sample programs provided in the Software Installation 
Package [link]. 

Tip: 

Taking data from every channel can be as simple as calling “ADC_GetImmediateScanV(0, rangeCode, &data);”, which converts all 

channels at the specified range and stuffs the data 

(as double-precision floating point Voltages) into the data array.  This function can be called many thousands of times per second.  Please refer to the samples and the software reference 
for details on this and other available API functions, including how to acquire 1MHz data via callback or polling. 

Advanced Topics 

BASIC, ADVANCED, AND NON -SEQUENCED MODES  

The ADAS3022 uses the SEQ1:0 bits in the +38 and +3C control registers to select between non-sequenced mode, basic sequence mode, and advanced sequence mode. 

SEQ1  SEQ0  Mode 

Description 

non-Sequenced  

The ADAS will acquire data from the channel specified in the INx2:0 bits, at the gain specified in the Gain2:0 bits. 

Modify Basic 
Sequence 

Allows the gain and such to be modified while running a basic sequence, without starting conversions over at CH0. 

Advanced 
Sequence  

Acquires Channel 0 using the gain selected via +18 bits 2:0.  Conversion-starts will automatically cycle through the channels from CH0 through INx2:0, 
and each channel is acquired at the per-channel gain set in +18.  The sequence repeats, starting at CH0 after INx2:0 is acquired. 

Basic Sequence  

Acquires channel 0 using the gain set in Gain2:0.  Conversion-starts will automatically cycle through the channels from CH0 through INx2:0, but all 
channels are acquired using the gain set in Gain2:0 rather than using the gains from +18. The sequence repeats, starting at CH0 after INx2:0 is 
acquired. 

SOFTWARE, PERIODIC, AND EXTERNAL  START ADC CONVERSION TIMING MODES  

ADC data can be acquired periodically, synchronous to an external digital input, or asynchronously via software command. 

Single, Asynchronous: If the +10 ADC Timing divisor is zero then writing to +38 or +3C with bit 16 set (to 1) will initiate a single ADC Start Event under software control. 

Periodic, Asynchronous: If the +10 ADC Timing divisor is non-zero, and the External ADC Trigger Digital Input Secondary function is 

not

 enabled, writing to +38 with bit 16 set will initiate a 

single ADC Start Event, and subsequent events will occur at the rate selected via +10’s divisor.

  

This is “software initiated periodic timed ADC” data.  Note: con3C before this write 

to +38. 

External Trigger, Periodic, Synchronous: If the +10 ADC Timing divisor is non-zero, and the External ADC Trigger Digital Input Secondary function 

is

 enabled, writing to +38 with bit 16 set 

ARMS

 the card to begin the periodic collection of ADC data.  No data will be collected until the selected edge occurs on the ADC Trigger input. (Refer to +44 for additional details on the 

Digital I/O Secondary Functions.)  Once triggered, data will be collected until manually stopped by w38 with bit 16 clear (or various resets, etc.). 

External Start, Single, Sy

nchronous: The digital input secondary function “ADC Start” can be configured to initiate individual ADC Start Events on a se

lected edge input. 

Содержание M.2-AI12-16

Страница 1: ...t 800 326 1649 http accesio com mPCIe AIO16 16F http accesio com M 2 AIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 2 DIGITAL I O FOR M 2 AND PCI EXPRESS MINI CARD HARDWARE MANUAL MODELS M 2 AND MPCIE AIO16 16F FAMILY ...

Страница 2: ... to 10V 2 5V 5V 10V Outputs Drive 10mA Guaranteed FDS models support Waveform playback on 1 2 3 or 4 DACs simultaneously at up to 1MHz aggregate Onboard Watchdog with status output RoHS compliant standard CHAPTER 3 HARDWARE This manual applies to the following models VENDEV M 2 mPCIe AIO16 16FDS A D 16 bit 2Msps 4 D A w timed DAC Waveform playback 494F C0EB M 2 mPCIe AIO16 16F A D 16 bit 2Msps 4 D...

Страница 3: ...milar devices where physical dimension is often the paramount design constraint In Data Acquisition and Control applications low weight and vibration tolerance tend to be of more concern CHAPTER 6 I O INTERFACE Most customers will use the optional cable assembly CAB mPCIe AIOs D Sub Miniature 37 pin Male connector For Singled Ended analog inputs connect GND to ADC COMMON A Note About Unused Analog...

Страница 4: ...er at CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquired at the per channel gain set in 18 The sequence repeats starting at CH0 after INx2 0 is acquired 1 1 Basic Sequence Acquires channel 0 using the gain set in Gain2 0 Conversion starts will autom...

Страница 5: ...n control bit and status 4 RW DAC Control Status DAC LTC2664 Command Register bits and DAC status bits 8 W DAC Waveform Divisor DAC Waveform Points second divisor Base Clock DAC Waveform Rate this register C R Base Clock Frequency of the ADC Sequencer Base Clock Hz used to calculate the ADC Rate Divisor for desired conversion rates 10 W R ADC Rate Divisor ADC Start Rate Base Clock ADC Rate Divisor...

Страница 6: ... will reset the Analog Input circuits to their power on reset state see each ADC Register for more details RST BOARD Writing a 1 will reset the entire device to its power on reset state All RST bits are command bits a 1 causes the reset to occur and the reset clears the 1 DAC Control Offset 4 of 32 bit Memory BAR 1 Read Write 32 bits only bit D31 D30 D29 D28 D27 D24 D23 through D20 D19 through D16...

Страница 7: ...te 32 bits only bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 7 GAIN2 0 RSV AIN 6 GAIN2 0 RSV AIN 5 GAIN2 0 RSV AIN 4 GAIN2 0 RSV AIN 3 GAIN2 0 RSV AIN 2 GAIN2 0 RSV AIN 1 GAIN2 0 RSV AIN 0 GAIN2 0 Each nybble configures the gain of the corresponding Analog Input channel ONLY when the ADC is running in Advance...

Страница 8: ...NUSED 0 VALID RSV DIO1 DIO0 RSV RSV TEMP MUX SEQ Channel2 0 Diff Gain2 0 ADC Counts Two s complement ADC FIFO Data Read the RAW format ADC Conversion results in twos complement 16 bit form and the associated status word INVALID If INVALID is SET then all other bits are undefined and the entry should be discarded This can occur if you read from the ADC FIFO while the ADC FIFO Count 28 is zero RUNNI...

Страница 9: ... differential mode is set and each conversion will be the measurement between the IN and IN pins Gain2 0 If BASIC or non sequenced mode is configured via the SEQ1 0 bits then Gain2 0 selects the gain to be used for the conversion s commanded If advanced sequence mode is configured then these bits are ignored bits 2 0 at 18 take precedence in advanced sequencer mode MUX All users should set this bi...

Страница 10: ...ite 32 bits only bit D31 through D2 D1 D0 Name UNUSED DIO1 DIO0 Read DIO Data to read the digital input pins or to readback the last commanded digital output state Write to DIO Data to configure the digital pin s high low state for those bits in I O Groups configured as Outputs SET bits will output high voltage CLEAR bits will output GND Refer to DIO Control 48 for how to configure the input vs ou...

Страница 11: ... bits only DAC Waveform FIFO Write DAC commands to load the DAC Waveform FIFO Generally 0x000nCCCC where n is the DAC and CCCC is the counts Read returns the number of control values currently in the FIFO FDS models only DAC Waveform DACs Point Offset 54 of 64 bit Memory BAR 2 3 Read Write 32 bits only DAC Waveform DACs Point Write 1 2 3 or 4 to specify how many DACs are being used for Waveform Pl...

Страница 12: ... can see an additional 7µs per transaction a modern computer might see 3µs or less Any transaction from the kernel itself however avoids this additional overhead Real time operating systems will enable the highest transaction rates possible all the way up to the hardware limits The latest information can always be found on the product page on the website Here are some useful links Links to useful ...

Страница 13: ...ting Female D Sub Miniature 37 pin Model Options T Extended Temperature Operation 40 to 85 C I ID 4 20mA inputs Singled ended Differential PD Pull downs on digital bits Sxx Special configurations 10 50mA inputs input voltage dividers conformal coating etc CHAPTER 9 CERTIFICATIONS CE FCC These devices are designed to meet all applicable EM interference and emission standards However as they are int...

Страница 14: ... package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will be returned to the customer s user s site freight prepaid and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with ...

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