background image

 

ACCES I/O Products, Inc. 

MADE IN THE USA 

mPCIe- and M.2-AIO16-16F Family Manual 

 

Rev B7a 

 

ADC Counts: 

16-

bit two’s complement ADC counts, the ADC conversion result from the samples Channel at the specified Gain, sampled in Differe

ntial or Singled-ended / 

Pseudo-Differential mode as indicated by the Diff bit (D19). 

Please refer to the “Software Tips” section for details on how to translate RAW

-format ADC data into Volts 

 or skip the hassle and use our AIOAIO.dll API Library: 

 

ADC_GetImmediateV(iBoard, pVolts, iChannel, iRange);,  ADC_GetImmediateScanV(iBoard, pVolts[]); etc. 

 

ADC Control, 38 of 32-bit Memory BAR[1]Read/Write 32-bits only 

bit  D31 through D19 

D18 

D17 

D16  D15  D14 through D12 

D11 

D10  D9 through D7  D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name  UNUSED 

SCAN 

CONFIG 

GO 

RSV 

IN

x

2:0 

COM 

RSV 

Gain2:0 

/MUX  SEQ1 

SEQ0 

/TEMP  RSV  CMS 

RSV 

Controls ADAS #0, channels 0-7 

The ADAS3022 is a very flexible ADC module and we highly recommend you use the AIOAIO.dll-provided API to avoid needing to know the following information. 

SCAN:   If SCAN is set (to 1) 

AND

 INx2:0 is non-

zero then each “ADC Start” event will acquire channels 0 through INx2:0 at the rate specified in +14.

 

CONFIG: If CONFIG is set then the ADC control bits (D15 through D0 of this register) will be written to the ADAS3022 

GO: 

If GO is set then, if +10 is non-zero the card will begin taking ADC conversions or scans at the rate set via +10; if +10 is zero then a single ADC conversion or scan will be 
taken. 

INx2:0:  INx specifies the individual channel to convert (in non-sequenced modes) or the last channel of the 0-INx sequence to be converted. 

COM: 

If COM is set then each conversion will be the measurement between the IN+ pin and COMMON (single-ended or pseudo-differential mode).  If COM is clear then 
differential mode is set, and each conversion will be the measurement between the IN+ and IN- pins. 

Gain2:0: If BASIC or non-sequenced mode is configured via the SEQ1:0 bits then Gain2:0 selects the gain to be used for the conversion(s) commanded.  If advanced sequence 

mode is configured then these bits are ignored (bits 2:0 at +18 take precedence in advanced sequencer mode) 

/MUX: 

All users should set this bit to “1” unless otherwise instructed by the factory.  If MUX is clear (0) then the conversion wil

l be from the auxiliary mux inputs (in non-

sequencer mode) or the sequence will include the aux input (sequencer modes).  Not recommended. 

SEQ1:0:  

Use “00” for non

-

sequenced mode and “10” for advanced sequencer mode.  “11” sets basic sequencer mode, and “01” updates the basic sequence

-in-progress.  Not 

recommended. 

/TEMP:  If TEMP is clear (0) then the conversion will be from the onboard temperature reference (in non-sequencer mode) or the sequence will include the temperature input 

(sequencer modes). Not recommended. Most users should set this bit to 1. 

CMS: 

Must be set if conversion will occur slower than 1kHz. Must be clear if conversions will occur faster than 900kHz. 

ADC Control #2, 3C of 32-bit Memory BAR[1]Read/Write 32-bits only 

bit  D31 through D19 

D18 

D17 

D16  D15  D14 through D12 

D11 

D10  D9 through D7  D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name  UNUSED 

RSV 

CONFIG 

RSV 

RSV 

IN

x

2:0 

COM 

RSV 

Gain2:0 

/MUX  SEQ1 

SEQ0 

/TEMP  RSV  CMS 

RSV 

Controls ADAS #1, channels 8-15.  Refer to +38, ADC Control #1, for details.   
 

 

IRQ Enable/Clear and Status, 40 of 64-bit Memory BAR[2+3] Read/Write 32-bits only 

bit  D31  

D30 … 

D25 

D24  D23  D22  D21  D20  D19  D18 

D17 

D16 

D15 … 

D10 

D9 

D8 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name  WDG  UNUSED  EXT1  EXT0  LDAC  FOF  FAF  DTO  DDONE  ADCSTART  ADCTRIG  UNUSED  enDACFHE  enEXT1  enEXT0  enLDAC  enFOF  enFAF  enDTO  enDDONE  enADCSTART  enADCTRIG 

Read IRQ Status to determine which/if any IRQs have fired (D23…D16), if the Watchdog has Barked (D31), and which IRQs are ena

bled (D9

…D0):

 

Содержание M.2-AI12-16

Страница 1: ...t 800 326 1649 http accesio com mPCIe AIO16 16F http accesio com M 2 AIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 2 DIGITAL I O FOR M 2 AND PCI EXPRESS MINI CARD HARDWARE MANUAL MODELS M 2 AND MPCIE AIO16 16F FAMILY ...

Страница 2: ... to 10V 2 5V 5V 10V Outputs Drive 10mA Guaranteed FDS models support Waveform playback on 1 2 3 or 4 DACs simultaneously at up to 1MHz aggregate Onboard Watchdog with status output RoHS compliant standard CHAPTER 3 HARDWARE This manual applies to the following models VENDEV M 2 mPCIe AIO16 16FDS A D 16 bit 2Msps 4 D A w timed DAC Waveform playback 494F C0EB M 2 mPCIe AIO16 16F A D 16 bit 2Msps 4 D...

Страница 3: ...milar devices where physical dimension is often the paramount design constraint In Data Acquisition and Control applications low weight and vibration tolerance tend to be of more concern CHAPTER 6 I O INTERFACE Most customers will use the optional cable assembly CAB mPCIe AIOs D Sub Miniature 37 pin Male connector For Singled Ended analog inputs connect GND to ADC COMMON A Note About Unused Analog...

Страница 4: ...er at CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquired at the per channel gain set in 18 The sequence repeats starting at CH0 after INx2 0 is acquired 1 1 Basic Sequence Acquires channel 0 using the gain set in Gain2 0 Conversion starts will autom...

Страница 5: ...n control bit and status 4 RW DAC Control Status DAC LTC2664 Command Register bits and DAC status bits 8 W DAC Waveform Divisor DAC Waveform Points second divisor Base Clock DAC Waveform Rate this register C R Base Clock Frequency of the ADC Sequencer Base Clock Hz used to calculate the ADC Rate Divisor for desired conversion rates 10 W R ADC Rate Divisor ADC Start Rate Base Clock ADC Rate Divisor...

Страница 6: ... will reset the Analog Input circuits to their power on reset state see each ADC Register for more details RST BOARD Writing a 1 will reset the entire device to its power on reset state All RST bits are command bits a 1 causes the reset to occur and the reset clears the 1 DAC Control Offset 4 of 32 bit Memory BAR 1 Read Write 32 bits only bit D31 D30 D29 D28 D27 D24 D23 through D20 D19 through D16...

Страница 7: ...te 32 bits only bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 7 GAIN2 0 RSV AIN 6 GAIN2 0 RSV AIN 5 GAIN2 0 RSV AIN 4 GAIN2 0 RSV AIN 3 GAIN2 0 RSV AIN 2 GAIN2 0 RSV AIN 1 GAIN2 0 RSV AIN 0 GAIN2 0 Each nybble configures the gain of the corresponding Analog Input channel ONLY when the ADC is running in Advance...

Страница 8: ...NUSED 0 VALID RSV DIO1 DIO0 RSV RSV TEMP MUX SEQ Channel2 0 Diff Gain2 0 ADC Counts Two s complement ADC FIFO Data Read the RAW format ADC Conversion results in twos complement 16 bit form and the associated status word INVALID If INVALID is SET then all other bits are undefined and the entry should be discarded This can occur if you read from the ADC FIFO while the ADC FIFO Count 28 is zero RUNNI...

Страница 9: ... differential mode is set and each conversion will be the measurement between the IN and IN pins Gain2 0 If BASIC or non sequenced mode is configured via the SEQ1 0 bits then Gain2 0 selects the gain to be used for the conversion s commanded If advanced sequence mode is configured then these bits are ignored bits 2 0 at 18 take precedence in advanced sequencer mode MUX All users should set this bi...

Страница 10: ...ite 32 bits only bit D31 through D2 D1 D0 Name UNUSED DIO1 DIO0 Read DIO Data to read the digital input pins or to readback the last commanded digital output state Write to DIO Data to configure the digital pin s high low state for those bits in I O Groups configured as Outputs SET bits will output high voltage CLEAR bits will output GND Refer to DIO Control 48 for how to configure the input vs ou...

Страница 11: ... bits only DAC Waveform FIFO Write DAC commands to load the DAC Waveform FIFO Generally 0x000nCCCC where n is the DAC and CCCC is the counts Read returns the number of control values currently in the FIFO FDS models only DAC Waveform DACs Point Offset 54 of 64 bit Memory BAR 2 3 Read Write 32 bits only DAC Waveform DACs Point Write 1 2 3 or 4 to specify how many DACs are being used for Waveform Pl...

Страница 12: ... can see an additional 7µs per transaction a modern computer might see 3µs or less Any transaction from the kernel itself however avoids this additional overhead Real time operating systems will enable the highest transaction rates possible all the way up to the hardware limits The latest information can always be found on the product page on the website Here are some useful links Links to useful ...

Страница 13: ...ting Female D Sub Miniature 37 pin Model Options T Extended Temperature Operation 40 to 85 C I ID 4 20mA inputs Singled ended Differential PD Pull downs on digital bits Sxx Special configurations 10 50mA inputs input voltage dividers conformal coating etc CHAPTER 9 CERTIFICATIONS CE FCC These devices are designed to meet all applicable EM interference and emission standards However as they are int...

Страница 14: ... package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will be returned to the customer s user s site freight prepaid and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with ...

Отзывы: