2-10
FP-IN9 SLI
2.4 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
►
Memory Timing Setting
Press Enter
Item Help
SLI Broadcast Aperture
Disabled
LDT Frequency
5x
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Memory Timing Setting
Click <Enter> key to enter its submenu:
Phoenix – AwardBIOS CMOS Setup Utility
Memory Timing Setting
Parameters
Setting
Current Value
Item Help
Memory Timing Setting
Auto
x tCL (CAS Latency)
Auto(5)
5
x tRCD
Auto(5)
5
x tRP
Auto(5)
5
x tRAS
Auto(18)
18
x Command Per Clock (CMD)
Auto(2T)
2T
** Advance Memory Settings **
x tRRD
Auto(3)
3
x tRC
Auto(22)
22
x tWR
Auto(5)
5
x tWTR
Auto(9)
9
x tREF
Auto
7.8uS
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Memory Timing Setting
You may manually set the DRAM timing parameters through the following sub-items, or leave
them at their default settings according to the SPD (Serial Presence Detect) data stored in the
DRAM.
-
tCL (CAS Latency)
- tRCD
- tRP
- tRAS
-
Command Per Clock (CMD)
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