TRIPL1
BLOCK
AND
L1TRIP
t
tEvolvingFault
t
tTripMin
L2TRIP
L3TRIP
P3PTR
OR
OR
OR
AND
TRIP
IEC17000065-2-en.vsdx
IEC17000065 V2 EN-US
Figure 218:
Simplified additional logic per phase, Program = 1ph/3ph or
1ph/2ph/3ph
IEC17000066=1=en=Original.vsdx
TRL1
t
3ms
BLKLKOUT
OR
OR
TRIPL1
AND
TRIPL3
TRIPL2
TRIPALL
TRL2
TRL3
-LOOP
AND
-LOOP
OR
AND
OR
OR
OR
OR
AND
AND
OR
AND
AND
OR
t
10 ms
t
5 ms
TR3P
AND
OR
SETLKOUT
RSTLKOUT
AND
OR
-LOOP
-LOOP
AND
AND
TR1P
TR2P
CLKLKOUT
AutoLock
TripLockout
TRIP
To ensure that the
fault is single phase
To ensure that the
fault is two phase
IEC17000066 V1 EN-US
Figure 219:
Final tripping circuits
1MRK 505 394-UEN A
Section 14
Logic
Line differential protection RED650 2.2 IEC
439
Technical manual
Содержание RED650
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