bdi
GDB
for BDI3000 (QorIQ P3/P4/P5)
User Manual
32
© Copyright 1997-2012 by ABATRON AG Switzerland
V 1.03
Supported standard parallel NOR Flash Memories:
There are different flash algorithm supported. Almost all currently available parallel NOR flash mem-
ories can be programmed with one of these algorithm. The flash type selects the appropriate algo-
rithm and gives additional information about the used flash.
On our web site (www.abatron.ch -> Debugger Support -> GNU Support -> Flash Support) there is a
PDF document available that shows the supported parallel NOR flash memories.
Some newer Spansion MirrorBit flashes cannot be programmed with the MIRRORX16 algorithm be-
cause of the used unlock address offset. Use S29M32X16 for these flashes.
The AMD and AT49 algorithm are almost the same. The only difference is, that the AT49 algorithm
does not check for the AMD status bit 5 (Exceeded Timing Limits).
Only the AMD and AT49 algorithm support chip erase. Block erase is only supported with the AT49
algorithm. If the algorithm does not support the selected mode, sector erase is performed. If the chip
does not support the selected mode, erasing will fail. The erase command sequence is different only
in the 6th write cycle. Depending on the selected mode, the following data is written in this cycle (see
also flash data sheets): 0x10 for chip erase, 0x30 for sector erase, 0x50 for block erase.
To speed up programming of Intel Strata Flash and AMD MirrorBit Flash, an additional algorithm is
implemented that makes use of the write buffer. The Strata algorithm needs a workspace, otherwise
the standard Intel algorithm is used.