bdi
GDB
for BDI3000 (QorIQ P3/P4/P5)
User Manual
34
© Copyright 1997-2012 by ABATRON AG Switzerland
V 1.03
3.2.5 Part [REGS]
In order to make it easier to access target registers via the Telnet interface, the BDI can read in a
register definition file. In this file, the user defines a name for the register and how the BDI should
access it (e.g. as memory mapped, memory mapped with offset, ...). The name of the register defi-
nition file and information for different registers type has to be defined in the configuration file. The
register name, type, address/offset/number and size are defined in a separate register definition file.
An entry in the register definition file has the following syntax:
name
type
addr
[size [SWAP]]
name
The name of the register (max. 15 characters)
type
The register type
GPR
General purpose register
SPR
Special purpose register
PMR
Performance monitor register
CCSR
Relative to CCSRBAR memory mapped register.
DCSR
Memory mapped register in DCSR space
MM
Absolute direct memory mapped register
DMM1...DMM4 Relative direct memory mapped register
IMM1...IMM4
Indirect memory mapped register
addr
The address, offset or number of the register
size
The size (8, 16, 32) of the register (default is 32)
SWAP
If present, the bytes of a 16bit or 32bit register are swapped. This is useful
to access little endian ordered registers (e.g. PCI bridge configuration reg-
isters).
The following entries are supported in the [REGS] part of the configuration file:
FILE filename
The name of the register definition file. This name is used to access the
file via TFTP. The file is loaded once during BDI startup.
filename
the filename including the full path
Example:
FILE C:\bdi\regs\regP4080.def
DMMn base
This defines the base address of direct memory mapped registers. This
base address is added to the individual offset of the register.
base
the base address
Example:
DMM1 0x01000
IMMn addr data
This defines the addresses of the memory mapped address and data reg-
isters of indirect memory mapped registers. The address of a IMMn regis-
ter is first written to "addr" and then the register value is access using
"data" as address.
addr
the address of the Address register
data
the address of the Data register
Example:
DMM1 0x04700000
Remark:
The registers
msr
,
cr, pc, pc64, iar, iar64
and
fpscr
and are predefined.