Aastra X Series, Руководство по установке и внедрению

Страница: 126 / 217

AMT/PTD/TR/0020/2/7/EN 10/2008 Page 6-126
6.5 Means of LDT/LDS card diagnosis on NeXspan 50
The method used to check that the LDT/LDS card configuration and wiring of DECT
synchronisation clocks are correct is based on the reading of the content of certain registers
accessible on these cards.
The accessible registers are not the same for the LDT card and LDS card.
The vport command must be used with “enter command” with the following syntax:
VPORT ADR=aaaa GP=xx CLX=y
where: aaaa=register I/O address
xx=Cluster number
y=LDT/LDS card number
6.5.1 Reading of the LDT card register content
CFG REGISTER
I/O address = 5010H
NF0=1: new daughter card for signal processing available (channels 0-7)
NF1=1: new daughter card for signal processing available (channels 8-15)
SPH=1: advance or lateness above 16 clock bit periods.
POLHRAD=1: bad DECT clock polarity.
ABSHDECT=1: absence of DECT clock on the LDT card input.
Note:
The SPH, POLHRAD and ABSHDECT bits are reset to 0 by reading the register.
RNBRESYNC REGISTER
I/O address = 5032H