AD484 user manual
V1.2
AD484 User manual
February 2007
www.4dsp.com
- 7 -
3.1.1.4
PCI interface
The Virtex-4 device A interfaces directly to the PCI bus via the PMC Pn1, Pn2 and Pn3
connectors or to the PCI-e bus via the Pn5. An embedded PCI core from Xilinx is used to
communicate over the PCI bus with the host system on the motherboard. PCI-e 4 lanes, PCI-
X 64-bit 66MHz/133MHz, PCI 64-bit 66MHz and PCI 32-bit 33MHz are supported on the
AD484. The bus type must be communicated at the time of the order so the right Virtex-4
device A firmware can be loaded into the flash prior to delivery.
The following performances have been recorded with the AD484 transferring data on the
bus:
PCI-X 64-bit 133MHz: 750Mbytes/s sustained
PCI-X 64-bit 66MHz: 425Mbytes/s sustained
PCI 32-bit 33MHz: 112Mbytes/s sustained
The PCI-express 4-lane is using the MGT I/Os on the Virtex-4 device A. Power filtering, low
jitter clock and special routing are used to achieve the performances required by this
standard. Please refer to the Front Panel Optical transceivers section of this document for
more details (3.6).
3.1.1.5
LED
Four LEDs are connected to the Virtex-4 device A. In the default FPGA firmware, the LEDs
are driven by the Virtex-4 device B via the Virtex-4 device A/ Virtex-4 device B interface.
The LEDs are located on side 2 of the PCB in the front panel area.
Figure 2: FPGA LED locations
