AD484 user manual
V1.2
AD484 User manual
February 2007
www.4dsp.com
- 13 -
3.3 Clock tree
The AD484 clock architecture offers an efficient distribution of low jitter clocks. In addition to
the PCI Express bus, the MGT reference clocks of 106.25MHz and 125MHz (Epson
EG2121CA) make it possible to implement several standards over the MGT I/Os connected
to the optical transceivers.
Both FPGAs receive a low jitter 125MHz clock. A low jitter programmable clock able to
generate frequencies from 62.5MHz to 255.5MHz in steps of 0.5MHz is also available. This
clock management approach ensures maximum flexibility to efficiently implement multi-clock
domains algorithms and use the memory devices at different frequencies. Both clock buffer
devices (CDM1804) and the frequency synthesizer (ICS8430-61) are controlled by the
Virtex-4 device A.
Figure 7 : Clock tree
3.4 Memory resources
3.4.1 QDR2 SRAM
Four independent QDR2 SRAM devices are connected to the Virtex-4 device B. The QDR2
SRAM devices available on the AD484 are 2M words deep (8Mbytes per memory device).
Please note that only three QDR SRAM devices are available to the user if the XC4VLX40,
XC4VLX60 or XC4VSX55 FPGA device is mounted on board.
3.4.2 DDR2 SDRAM
Two 16-bit DDR2 SDRAM devices of 128MBytes each are connected to Virtex-4 device A.
The two memories share the same address and control bus and have their own data bus.
This memory resource can be accessed by the PowerPC processor in the Virtex-4 device A
or can be used as a data buffer for custom user logic.
