AD484 user manual
V1.2
AD484 User manual
February 2007
www.4dsp.com
- 6 -
The AD484 converts 4 analogue signals into four 14-bit resolution digital data flows with a
sampling frequency up to 125MHz. The clock source can be set to external or internal using
the software and firmware settings available to users. Please note that the clock generation
on board is using low-jitter clock synthesizers.
2 Installation
2.1 Requirements and handling instructions
The AD484 must be installed on a motherboard compliant to the IEEE Std 1386-2001
standard for 3.3V PMC or on a motherboard compliant to the XMC Switched
Mezzanine Card Auxiliary Standard
Do not flex the board
Observe SSD precautions when handling the board to prevent electrostatic
discharges.
Do not install the AD484 while the motherboard is powered up.
2.2 Firmware and software
Drivers, API libraries and a program example working in combination with a pre-programmed
firmware for both FPGAs are provided. The AD484 is delivered with an interface to the Xilinx
PCI core in the Virtex-4 device A and an example VHDL design in the Virtex-4 device B so
users can start digitizing and performing data manipulation right out of the box. For more
information about software installation and FPGA firmware, please refer the AD484 Get
Started Guide and to the Programmer
’
s guide available online.
3 Design
3.1 FPGA devices
The Virtex-4 FPGA devices interface to the various resources on the AD484 as shown on
Figure 1. They also interconnect to each other via 86 general purpose pins and 2 clock pins.
3.1.1 Virtex-4 device A
3.1.1.1
Virtex-4 device A family and package
The Virtex-4 device A is from the Virtex-4 FX family. It can be either an XC4VFX20 or
XC4VFX60 in a Fineline Ball Grid array with 672 balls (FF672).
3.1.1.2
Power PC embedded processor
Up to two IBM PowerPC RISC processor cores are available in the Virtex-4 device A. This
core can be used to execute C based algorithms and control the logic resources
implemented in the FPGA.
3.1.1.3
Virtex-4 device A external memory interfaces
The Virtex-4 device A is connected to a 128Mbytes SDRAM bank with a 32-bit data bus
width. This memory resource can be used by the PowerPC core or can serve as data buffer.
