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CPU

User Manual

UM001604-0108

Instruction Description

246

Example 1

If Working Register R3 contains

45h

(

01000101b

) and Working Register R7 contains the

value

02h

(

00000010b

) (bit 1 is being tested if it is 0), the statement:

TM R3, R7

Op Code: 72 37

sets the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are
cleared.

Example 2

Working Register R14 contains the value

F3h

(

11110011b

), Working Register R5 con-

tains

CBh

, and Register

CBh

contains

88h

(

10001000b

) (bit 7 a bit 3 are being tested if

they are 0), the statement:

TM R14, @R5

Op Code: 73 E5

resets the Z Flag, because bit 7 in the destination operand is not a 0. The S Flag is set, and
the V Flag is cleared.

Example 3

If Register

D4h

contains the value

08h

(

00001000b

), and Working Register R0 contains

the value

04h

(

00000100b

) (bit 2 is being tested if it is 0), the statement:

TM D4h, R0

Op Code: 74 E0 D4

sets the Z Flag, because bit 2 in the destination operand is a 0. The S and V Flags is
cleared.

Example 4

If Register

DFh

contains the value

←

(

00000000b

), Register

07h

contains the value

1Fh

and Register

1Fh

contains the value

BDh

(

10111101b

) (bit 7, bit 5, bit 4, bit 3, bit 2, and

bit 0 are being tested if they are 0), the statement:

TM DFh, @07h

Op Code: 75 07 DF

sets the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and
the V Flag is cleared.

Example 5

If Working Register R13 contains the value

F1h

(

11110001b

), the statement:

TM R13, #02h

Op Code: 76 ED, 02

Summary of Contents for Z8 CPU

Page 2: ...reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Document Disclaimer 2008 by Zilog Inc All rights reserved Information in this pub...

Page 3: ...re details refer to the corresponding pages and appropriate links in the table below Date Revision Level Description Page No January 2008 04 Updated Zilog logo Zilog text Disclaimer section and implem...

Page 4: ...and Peripheral Registers 15 Standard Z8 Registers 15 Expanded Z8 Registers 16 Program Memory 19 Z8 External Memory 20 External Data Memory 21 Z8 Stacks 22 Clock 24 Frequency Control 24 Clock Control 2...

Page 5: ...ort 3 56 General Port I O 56 Read Write Operations 61 Special Functions 61 Port Handshake 63 I O Port Reset Conditions 66 Full Reset 66 Analog Comparators 68 Comparator Description 68 Comparator Progr...

Page 6: ...y Register Initialization 100 Interrupt Mask Register Initialization 101 Interrupt Request Register Initialization 102 IRQ Software Interrupt Generation 104 Vectored Processing 105 Vectored Interrupt...

Page 7: ...nal Stacks 133 Data Memory 134 Bus Operation 134 Address Strobe 136 Data Strobe 136 Extended Bus Timing 137 Instruction Timing 138 Z8 Reset Conditions 140 Instruction Set 141 Processor Flags 144 Carry...

Page 8: ...s or outputs Outputs are software programmable as open drain or push pull on a port basis Inputs are Schmitt Triggered with autolatches to hold unused inputs at a known voltage state Analog Inputs Thr...

Page 9: ...s new option provides for reduced radiated emission via clock and output drive circuit changes Low Power CMOS with two standby modes STOP and HALT Full Z8 Instruction Set Forty eight basic instruction...

Page 10: ...Technical Library Z8 CCP User Manual Table 1 Zilog General Purpose Microcontroller Product Family Product ROM RAM I O T C AN INT WDT POR VBO RC Speed MHz Pin Count Z86C03 512 60 14 1 2 6 F Y Y Y 8 18...

Page 11: ...Overview 4 A Z8 CCP Emulator Accessory Kit Z8CCP00ZAC is also available and provides an RS 232 cable and power cable along with the 28 and 40 pin ZIF sockets and 28 and 40 pin target connector cables...

Page 12: ...ns that hold data only whether internal or external Z8 CPU Standard Register File The Z8 Standard Register File totals up to 256 consecutive bytes Registers The register file consists of 4 I O ports 0...

Page 13: ...least significant byte LSB goes into the next higher odd num bered register See Figure 2 By using a logical instruction and a mask individual bits within registers can be accessed for bit set bit cle...

Page 14: ...working register number from 0h to Fh RAM Protect The upper portion of the register file address space 80h to EFh excluding the control reg isters may be protected from reading and writing The RAM Pro...

Page 15: ...he Register Pointer thus forming the 8 bit actual address Figure 4 on page 9 displays this operation Because working registers are typically specified by short format instructions there are fewer byte...

Page 16: ...truction short format Actual register address 76h FF F0 R7 R6 R5 R4 R3 R2 R1 R0 Specified Working Register Group R253 I O Ports Working Register Group 1 Working Register Group 0 Working Register Group...

Page 17: ...ach address bit location when reading Writing to bits that are defined as timer output serial output or handshake output has no effect The Z8 CPU instruction DJNZ uses any general purpose working regi...

Page 18: ...mplemented Figure 6 Expanded Register File Architecture Z8 Register File F 0F WDTMR Expanded Register FF 0F 7F F0 00 Expanded Register File Bank F F 0E Reserved F 0D Reserved F 0C Reserved F 0B SMR F...

Page 19: ...s the ERF Bank while the upper nibble determines the Working Register Group within the register file as displayed in Figure 7 The value of the lower nibble in the Register Pointer FDh corresponds to t...

Page 20: ...File Bank C 1101b D Expanded Register File Bank D 1110b E Expanded Register File Bank E 1111b F Expanded Register File Bank F The Z8 Standard Register File is equivalent to Expanded Register File Ban...

Page 21: ...r accessible the selected ERF Bank Registers 00h to 0Fh are accessed instead It is important to re initialize the Regis ter Pointer to enable ERF Bank 0 when these registers are required for use The S...

Page 22: ...uest Register IRQ Table 7 Z8 ERF Bank Layout ERF Bank ERF Fh PCON SMR WDT 00h 0Bh 0Fh Working Register Group 0 only implemented Eh Not implemented reserved Dh Not implemented reserved Ch SPI Registers...

Page 23: ...E0 Timer Counter 1 T1 T1 Prescaler PRE1 Port 0 1 Mode P01M Port 2 Mode P2M Port 3 Mode P3M In addition the four port registers P0 P3 are considered to be peripheral registers Expanded Z8 Registers The...

Page 24: ...SPI Control SCON R2 1 SPI Tx Rx Data Roxburgh R1 0 SPI Compare SCOMP R0 Table 9 ERF Bank 0 WR Group 0 Register Function Working Register F General Purpose Register R15 E General Purpose Register R14...

Page 25: ...e Register R4 3 Port 3 R3 2 Port 2 R2 1 Port 1 R1 0 Port 0 R0 Table 10 ERF Bank F WR Group 0 Register Function Working Register F WDTMR R15 E Reserved R14 D Reserved R13 C Reserved R12 B SMR R11 A Res...

Page 26: ...m Memory fetches through Port 0 and Port 1 in Address Data mode for devices with Port 0 and Port 1 featured Otherwise the program counter continues to execute NOPs up to address FFFFh roll over to 000...

Page 27: ...external address is FFFF This memory interface is supported by the control lines AS Address Strobe DS Data Strobe and R W Read Write The origin of the external Program Memory starts after the last add...

Page 28: ...ish between data and Program Memory space The state of the DM signal is controlled by the type of instruction being executed An LDC opcode references Program Memory DM inactive and an LDE instruction...

Page 29: ...ck The Z8 CPU stack is a return stack for CALL instructions and interrupts as well as a data stack During a CALL instruction the contents of the PC are saved on the stack The PC is restored during a R...

Page 30: ...CPU User Manual UM001604 0108 Address Space 23 Figure 11 Stack Operations PCL Top of Stack Stack Contents PCH PCL PCH FLAGS After an Interrupt Cycle Stack Contents After a Call Instruction Top of Sta...

Page 31: ...ive and oscillator drive is reduced to approximately 25 percent of the standard drive and the divide by two flip flop is bypassed such that the XTAL clock frequency is equal to the internal system clo...

Page 32: ...is 0 SCLK System Clock and TCLK Timer Clock are equal to the external clock frequency divided by two The SCLK TCLK is equal to the external clock frequency when this bit is set D1 1 Using this bit tog...

Page 33: ...Expanded Register File Bank F Register 00h A 1 in bit D7 configures the oscillator with standard drive while a 0 configures the oscil lator with Low EMI drive This only affects the drive capability o...

Page 34: ...180 degree phase shift and the feedback element is forced to provide the other 180 degrees of phase shift R1 is a resistive component placed from output to input of the amplifier The purpose of this...

Page 35: ...o determine their reliability over full lot and temperature variations These two indicators are described below Start Up Time If start up time is excessive or varies widely from unit to unit there is...

Page 36: ...11 Crystal Resonator Characteristics Crystal Cut AT crystal only Mode Parallel Fundamental mode Crystal Capacitance 7pF Load Capacitance 10 pF CL 220 pF 15 typical Resistance 100 max XTAL2 VSS XTAL1...

Page 37: ...ceramic resonator manufacturer The RD can be increased to decrease the amount of drive from the oscillator output to the crystal It can also be used as an adjustment to avoid clip ping of the oscillat...

Page 38: ...put protection diode to VCC is not on XTAL1 Zilog recommends that in applications where the Z8 CPU is exposed to much system noise a diode from XTAL1 to VCC be used to prevent acciden tal enabling of...

Page 39: ...me cases the Z8 CPU features an RC oscillator option Refer to the specific product specification for availability The RC oscillator requires a resistor across XTAL1 and XTAL2 An additional load capaci...

Page 40: ...Stop Mode Recovery and WDT time out while in STOP mode While RESET pin is Low AS is output at the internal clock rate DS is forced Low and R W remains High The program counter is loaded with 000Ch I...

Page 41: ...U U U U U U U F3 T1 Prescaler U U U U U U 0 0 Single pass count mode external clock source F4 Counter Timer0 U U U U U U U U F5 T0 Prescaler U U U U U U U 0 Single pass count mode F6 Port 2 Mode 1 1 1...

Page 42: ...lly generated reset drives the reset pin low for the POR time Any devices driving the reset line must be open drained in order to avoid damage from possible conflict during reset conditions This reset...

Page 43: ...ort 2 U U U U U U U U Input mode output set to open drain 03 Port 3 1 1 1 1 U U U U Standard digital input and output Z86L7X Family Device Port P34 P37 0 Except Z86L70 71 75 All other Z8 1 04 EF Gener...

Page 44: ...1 1 1 0 Comparator outputs disabled on Port 3 Port 0 and 1 output is push pull Port 0 1 2 3 and oscillator with standard output drive 0B Stop Mode Recovery SMR 0 0 1 0 0 0 0 0 Clock divide by 16 off...

Page 45: ...6 512 1024 4096 WDT POR Counter Chain POR TpC TpC TpC TpC M WDT TAP SELECT Clear 18 Clock RESET RESET CLK Generator 4 Clock Filter CK CLR RC OSC U X Internal RESET 2 6 V Operating Voltage Det RESET Fr...

Page 46: ...5 ms 15 ms 25 ms 100 ms WDT POR Counter Chain CLK M WDT TAP SELECT 4 Clock Filter CLR Internal RC OSC U X 2 V Operating Voltage Det From Stop Mode Recovery Source Stop Delay Select SMR WDT VDD XTAL W...

Page 47: ...pin The POR clock source is selected with bit 4 of the Watchdog Timer Mode register WDTMR In some cases a Z8 that offers the WDT but does not have a WDTMR register has a fixed WDT time out and uses th...

Page 48: ...ock source to the POR counter A 1 indi cates active during STOP The default is 1 If bits D3 and D4 are both set to 1 the WDT only is driven by the external clock during STOP mode This feature makes it...

Page 49: ...Power fail to Power OK status cold start Stop Mode Recovery if bit 5 of SMR 1 WDT time out The POR time is specified as TPOR On Z8 devices that feature a Stop Mode Recovery register SMR bit 5 selects...

Page 50: ...puts of Port 2 can be turned OFF for open drain operation Mode Registers Each port has an associated Mode Register that determines the port s functions and allows dynamic change in port functions duri...

Page 51: ...e 29 on page 45 Because port inputs are asynchronous to the Z8 CPU internal clock a READ operation could occur during an input transition In this case the logic level might be uncertain between a logi...

Page 52: ...ly programmed as push pull or open drain Low EMI output buffers in some cases can be globally programmed by the software as an OTP program option or as a ROM mask option In such cases the Z8 MCU featu...

Page 53: ...put Ports 46 Figure 30 Port 0 Configuration with Open Drain Capability Autolatch and Schmitt Trigger OEN Port 1 I O or AD15 AD08 Handshake Controls DAV0 and RDY0 4 Z8 P32 and P35 PIN OUT IN 2 3 V Hyst...

Page 54: ...t be the same as the data in the output register Reading a nibble defined as input also returns data on the external pins However input bits under handshake control return data latched into the input...

Page 55: ...t bidirectional CMOS or TTL compatible port with multiplexed address A7 A0 and data D7 D0 ports These eight I O lines can be byte programmed as inputs or outputs or can be configured under software co...

Page 56: ...nfiguration with Open Drain Capability Autolatch and Schmitt Trigger D2 Write Only 0 P32 Input P35 Output Port 3 Mode Register P3M Register F7h 1 P32 DAV0 RDY0 P35 RDY0 DAV0 OEN Port 1 I O or AD7 AD0...

Page 57: ...nal pins is returned Under normal loading conditions this is equivalent to reading the output register However if Port 1 outputs are defined as open drain the data returned is the value forced on the...

Page 58: ...n Port 1 is an input port or RDY1 P33 and DAV1 P34 when Port 1 is an output port See Figure 37 through Figure 39 on page 53 Handshake direction is determined by the configuration input and output assi...

Page 59: ...be an input or output independently Input buffers can be Schmitt Triggered level shifted or a single trip point buffer and may contain autolatches Bits programmed as outputs may be globally programme...

Page 60: ...onfiguration with Open Drain Capability Autolatch and Schmitt Trigger Figure 40 Port 2 Configuration with TTL Level Shifter P21 P26 OE PIN P21 P26 OUT P21 P26 IN 2 3 V Hysteresis VCC 5 0 V OPEN DRAIN...

Page 61: ...ng P2 as the source register of an instruction When an output bit is read data on the external pin is returned Under normal loading conditions this is equivalent to reading the output register However...

Page 62: ...2 In this configuration Port 3 lines P31 and P36 are used as the handshake control lines DAV2 and RDY2 for input handshake or RDY2 and DAV2 for output handshake Handshake direction is determined by th...

Page 63: ...ured as special control lines for handshake comparator inputs SPI control external memory status or I O lines for the on board serial and timer facili ties Figure 44 on page 57 displays the block diag...

Page 64: ...utput Buffer Output Register Output Register Write Port Read Port 4 4 4 4 4 4 4 4 Internal Bus From Timer Handshake Logic or Serial I O To Interrupt Timer Handshake Logic or Serial I O Port Output Lin...

Page 65: ...parator Autolatch and Schmitt Trigger P31 AN1 R247 P3M IRQ2 TIN P31 Data Latch P30 1 Analog 0 Digital D1 R 500 K Autolatch Port 3 I O or Control P30 Data Latch IRQ3 Z8 P34 P35 P37 P36 P30 P31 P32 P33...

Page 66: ...r Manual UM001604 0108 Input Output Ports 59 Figure 46 Port 3 Configuration with Comparator PIN P37 0 P34 P37 Standard Output 1 P34 P37 Comparator Output D0 P37 OUT PCON P32 REF P33 PIN P34 P37 OUT P3...

Page 67: ...ut Ports 60 Figure 47 Port 3 Configuration with SPI and Comparator Outputs SPI MSTR PIN P31 SPI EN P34 SK IN SPI MSTR PIN P35 SPI EN REF SS 0 P34 P35 Standard Output 1 P34 P35 Comparator Output D0 P34...

Page 68: ...e output register Special Functions Special functions for Port 3 are defined by programming the Port 3 Mode Register By writing 0s in bit 6 through bit 1 lines P37 P30 are configured as input output p...

Page 69: ...Port 0 Handshake Input P32 DAV0 RDY0 Port 1 Handshake Input P33 DAV1 RDY1 Port 2 Handshake Input P31 DAV2 RDY2 D7 D6 D5 D4 D3 D2 D1 D0 Write Only 0 P31 P32 Digital Mode 1 P31 P32 Analog Mode 0 P32 Inp...

Page 70: ...input mode data is latched into the Port s input register by the first DAV signal and is protected from being overwritten if additional pulses occur on the DAV line This over write protection is main...

Page 71: ...uld not be changed until the handshake is completed Figure 50 and Figure 51 on page 65 display detailed operation for the handshake sequence Figure 50 Z8 Input Handshake Valid Data Input To Z8 State 1...

Page 72: ...tions Figure 51 Z8 Output Handshake Valid Data Input To Z8 State 1 2 1 3 4 5 RDY Output From Z8 DAV Output From Z8 Data on Port RDY input is High indicating that the I O device is ready to accept dat...

Page 73: ...out from Stop Mode Recovery does not do a full reset Cer tain registers that are not reset after Stop Mode Recovery will not be reset For the condition of the Ports after Stop Mode Recovery refer to t...

Page 74: ...rt 0 1 Reset Figure 55 Port 2 Reset Note 0 1 0 0 1 1 0 1 Write Only 01 Input 1X A8 A11 Stack Selection 0 External P00 P03 Mode 00 Output Port 0 1 Mode Register P01M Register F8h 01 Byte Output 1 Inter...

Page 75: ...comparators process analog signals on P31 and P32 with reference to the voltage on P33 The analog function is enabled by programming the Port 3 Mode Register P3M bit 1 For interrupt functions during a...

Page 76: ...analog or digital modes but it must be referenced to P33 when in analog mode Figure 57 Port 3 Input Analog Selection Figure 58 Port 3 Comparator Output Selection D1 Write Only 0 Digital Mode P31 P32 P...

Page 77: ...parator Inputs on P31 P32 and P33 P31 AN1 R247 P3M IRQ2 TIN P31 Data Latch P30 1 Analog 0 Digital D1 R 500 K Autolatch Port 3 I O or Control P30 Data Latch IRQ3 Z8 P34 P35 P37 P36 P30 P31 P32 P33 IRQ0...

Page 78: ...any binary number Example of enabling analog comparator output Figure 60 Port 3 Configuration LD P3M XXXX XX1Xb LD RP 0Fh Sets register pointer to working register group 0 and Expanded Register File B...

Page 79: ...puts are enabled to come out on P34 and P37 then P34 1 and P37 0 The previous data stored in P34 and P37 is not disturbed Once the comparator outputs are de selected the stored values in the P34 and P...

Page 80: ...able to generate interrupts Only P33 cannot generate an interrupt because the P33 input goes directly to the Ref input of the compara tors and is disconnected from the interrupt sensing circuits Stop...

Page 81: ...configuration register PCON The PCON register allows the oscillator and all I O ports to be programmed in the Low EMI Mode independently Other Z8 MCUs may offer a ROM Mask or OTP programming option to...

Page 82: ...rt 2 D5 can be configured as a Low EMI Port by resetting this bit D5 0 or configured as a Standard Port by setting this bit D5 1 The default value is 1 Low EMI Port 3 Port 3 D6 can be configured as a...

Page 83: ...diodes were removed on these pins to allow the application of 12 5 V during the various OTP programming modes For better noise immunity in applications that are exposed to system EMI a clamping diode...

Page 84: ...s straight forward Assume the input pad is latched at 5V logic 1 The inverter G1 inverts the bit turning the P channel FET ON and the N channel FET OFF The output of the circuit is effectively shorted...

Page 85: ...h imped ance state The autolatches then pull the input section toward VDD Autolatch Model The autolatch s equivalent circuit is displayed in Figure 66 When the input is high the circuit consists of a...

Page 86: ...nd the external pulldown forms a voltage divider and if the exter nal resistor is large the voltage developed across it will exceed VIL max For worst case VIL max VDD REXT REXT RP REXT max VIL max VDD...

Page 87: ...ware also controls the counting mode how a counter timer is started or stopped and its use of I O lines Both the counter and prescaler registers can be altered while the counter timer is running Count...

Page 88: ...n page 82 and Figure 71 on page 82 displays the prescaler registers The six most significant bits D2 D7 of PRE0 or PRE1 hold the prescalers count modulo a value from 1 to 64 decimal The prescaler regi...

Page 89: ...Write Only 1 T0 Modulo n Count Mode 0 T0 Single Pass Prescaler 0 Register R245 PRE0 01 00 HEX Prescaler Modulo Range 1 64 Decimal Reserved Must be 0 U U U U U U 0 0 F3 Write Only 1 T1 Modulo n Count...

Page 90: ...he Load bit for the next load operation New values may be loaded into the down counters at any time If the counter timer is running it continues to do so and starts the count over with the new value T...

Page 91: ...D1 of the TMR This loads the initial values of PRE0 and T0 into their respective counters and starts the count after the M2T2 machine state after the operand is fetched see Figure 74 Prescaler Operat...

Page 92: ...er continues its count value at the time it was stopped The current value in the Counter Timer can be read at any time without affecting the counting operation The prescaler registers are write only a...

Page 93: ...line by setting P3M bit 5 to 0 Output is controlled by one of the counter timers T0 or T1 or the internal clock The counter timer to be output is selected by TMR bit 7 and bit 6 T0 is selected to driv...

Page 94: ...unt the interrupt request line IRQ4 or IRQ5 clocks a toggle flip flop The output of this flip flop drives the TOUT line P36 In all cases when the selected counter timer reaches its end of count TOUT t...

Page 95: ...must be configured for external by setting the PRE1 Reg ister bit 2 to 1 The Timer Mode Register bit 5 and bit 4 can then be used to select the appropriate TIN operation For T1 to start counting as a...

Page 96: ...e TIN External Clock Input Mode TMR bit 5 and bit 4 both set to 0 supports counting of external events where an event is considered to be a High to Low transition on TIN see Figure 82 See the product...

Page 97: ...ount Triggered Input Mode The TIN Triggered Input Mode TMR bits 5 and 4 are set to 1 and 0 respectively causes T1 to start counting as the result of an external event see Figure 84 on page 91 T1 is th...

Page 98: ...t bit When enabled each High to Low TIN transition causes T1 to reload and restart counting Interrupt request IRQ5 is generated on every end of count Cascading Counter Timers For some applications it...

Page 99: ...et for External Clock mode and the TOUT mode is OFF Figure 87 on page 93 through Figure 89 on page 94 displays the binary reset values of the Prescaler Counter Timer and Timer Mode registers Figure 85...

Page 100: ...RITE ONLY 1 T1 MODULO N COUNT MODE 0 T1 SINGLE PASS PRESCALER 1 REGISTER R243 PRE1 01 00 HEX PRESCALER MODULO RANGE 1 64 DECIMAL CLOCK SOURCE 0 T1 EXTERNAL TIN 1 T1 INTERNAL U U U U U U U 0 F5 Write O...

Page 101: ...sable T0 Count 0 No Function 1 Load T0 Timer Mode Register R241 TMR 1 Enable T0 Count Retriggerable TOUT Modes Non retriggerable Trigger Input 10 TIN Modes External Clock Input 00 Gate Input 01 0 No F...

Page 102: ...able Interrupt DI instruction Interrupts are globally enabled by setting bit 7 with an Enable Interrupt EI instruction There are three interrupt control registers the Interrupt Request Register IRQ th...

Page 103: ...e exact interrupt sources supported Interrupt Sources Table 18 on page 97 describes the interrupt types sources and vectors available in the Z8 family of processors Figure 91 Interrupt Block Diagram I...

Page 104: ...rst flip flop is set The next two flip flops synchronize the request to the internal clock and delay it by two internal clock periods The output of the last flip flop IRQ0 IRQ1 or IRQ2 goes to the cor...

Page 105: ...the external sources so either an internal or external source can trigger the interrupt Internal interrupt sources and trigger conditions are device depen dent Refer to the device product specificatio...

Page 106: ...struction and written by specify ing it as the destination register Interrupt Initialization After reset all interrupts are disabled and must be initialized before vectored or polled interrupt process...

Page 107: ...n groups as listed in Table 19 on page 100 and Table 20 on page 101 Bits 1 2 and 5 define the priority of the individual members within the three groups Bits 0 3 and 4 are encoded to define six priori...

Page 108: ...set during an interrupt service routine and set following the execution of an Interrupt Return IRET instruction Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Regi...

Page 109: ...dis abled Before the IRQ register accepts requests it must be enabled by executing an ENABLE INTERRUPTS EI instruction Setting the Global Interrupt Enable bit in the Interrupt Mask Register IMR bit 7...

Page 110: ...device dependent When reserved the bits are not used and return a 0 when read When used as the Interrupt Edge select bits the configuration options are as listed in Table 21 on page 104 EI Enable IRQ...

Page 111: ...errupts SWI are controlled in the same manner as hardware generated requests in other words the IPR and the IMR control the priority and enabling of each SWI level Table 21 IRQ Register Configuration...

Page 112: ...are no higher priority pending requests control is transferred to the service routine pointed to by the IRQ5 vector Vectored Processing Each Z8 interrupt level has its own vector When an interrupt occ...

Page 113: ...U User Manual UM001604 0108 Interrupts 106 Figure 100 Effects of an Interrupt on the Stack SP Top of Stack PC LOW Byte PC HIGH Byte FLAGS SP and Stack after an interrupt SP SP and Stack before an inte...

Page 114: ...cuting instruction present in the user program assumes worst case condition of interrupt sampling Figure 95 on page 99 just prior to the interrupt occurrence To calculate the worst case interrupt late...

Page 115: ...vious mask from the stack Execute IRET Depending on the application some simplification of the above procedure may be possi ble Polled Processing Polled interrupt processing is supported by masking of...

Page 116: ...or returns back to the main program An example of a polling routine is as follows In this example if IRQ2 is being polled MASKA is 00000100b and MASKB is 11111011b Reset Conditions Upon reset all bits...

Page 117: ...program continues from the instruction after HALT HALT mode may also be exited via a POR RESET activation or a Watch Dog Timer WDT time out See the product data sheet for WDT availability In this case...

Page 118: ...mable set of inputs The selected Z8 device product specification should be reviewed to determine the SMR options available for use For devices that support SPI the slave mode compare feature also serv...

Page 119: ...Select This D0 bit of the SMR controls a divide by 16 prescaler of SCLK TCLK The purpose of this control is to selectively reduce device power consumption during normal processor execution SCLK contro...

Page 120: ...top Mode Recovery Edge Select A 1 in this D6 bit position indicates that a high level on any one of the recovery sources wakes the Z8 CPU from STOP mode A 0 indi cates low level recovery The default i...

Page 121: ...ior to entering STOP mode Figure 104 Stop Mode Recovery Source SMR D4 D3 D2 0 0 0 SMR D4 D3 D2 0 0 1 0 1 0 0 1 1 SMR D4 D3 D2 1 0 0 SMR D4 D3 D2 1 0 1 SMR D4 D3 D2 1 1 0 SMR D4 D3 D2 1 1 0 VDD P20 P23...

Page 122: ...ed by the Port 3 Mode P3M Register located at address F7h Z8 CPU always transmits eight bits between the start and stop bits eight Data Bits or seven Data Bits and one Parity Bit Odd parity generation...

Page 123: ...rate is given by the following equation Bit Rate XTAL Frequency 2 x 4 x p x t x 16 where p and t are the initial values in Prescaler0 and Counter Timer0 respectively The final divide by 16 is require...

Page 124: ...commonly used bit rates and the values of XTAL p and t required to derive them This list is presented for convenience and is not intended to be exhaustive Table 24 Bit Rates Bit Rate 7 3728 7 9872 9...

Page 125: ...clock by two D type flip flops before being input to the Shift Register and the start bit detection circuitry The start bit detection circuitry monitors the incoming data stream looking for a start b...

Page 126: ...the Interrupt Request Register must be reset by software Framing Errors Framing error detection is not supported by the receiver hardware but by responding to the interrupt request within one characte...

Page 127: ...ure 105 on page 115 After a hardware reset or after a character has been transmitted the transmitter is forced to a marking state output always High until a character is loaded into the transmitter bu...

Page 128: ...Request Register must be reset Parity The data format supported by the transmitter has a start bit eight data bits and at least two stop bits If parity is on bit 7 of the data transmitted will be repl...

Page 129: ...er microcontrollers and peripherals The SPI includes features such as Stop Figure 114 SIO Register Reset Figure 115 P3M Register Reset U U U U U U U U Read Write Serial Data D0 LSB Serial I O Register...

Page 130: ...in Master Mode select the clock rate You can choose whether internal clock is divide by 2 4 8 or 16 In Slave Mode Bit 1 of this register flags the user if an overrun of the RxBUF Register has occurre...

Page 131: ...TCLK for clocking the SPI Finally bit 7 determines whether the SPI is used as a Master or a Slave A 1 puts the SPI into Master mode and a 0 puts the SPI into Slave mode Figure 116 SPI Control Register...

Page 132: ...cycle Loading data into the shift register initiates the transfer In master mode the master s clock drives the slave s clock At the conclusion of a transfer a Receive Character Available RCA IRQ3 fla...

Page 133: ...ses and is reset when the RxBUF Register is read RxCharAvail is generated in both master and Figure 117 SPI System Configuration ss sk do di Slave Multiple slaves may have the same address ss1 ss4 do...

Page 134: ...data stream is received and loaded into the RxBUF Register Receive Character Overrun RxCharOver run occurs Because there is no requirement for clock control in slave mode bit D1 in the SPI Control Re...

Page 135: ...1604 0108 Serial Input Output 128 Figure 119 SPI Logic SPI Compare Register SCOMP SS D0 DI SK Port TCLK SMR Bit Control SPI Control SPI Receive Buffer RxBUF SPI Shift Register Interrupt Control IRQ3 S...

Page 136: ...PI Data In Out Configuration P27 OUT PIN SPI Active P27 IN 0 SOI D0 Enable OPEN DRAIN Autolatch P27 P20 OE PIN P20 IN OPEN DRAIN R 500 K Autolatch P20 SPI EN SPI DO P27 OE SPI SPI DO SPI Standard Stan...

Page 137: ...put Output 130 Figure 121 SPI Clock SPI Slave Select Output Configuration SPI MSTR PIN P31 SPI EN P34 SK IN SPI MSTR PIN P35 SPI EN REF SS 0 P34 P35 Standard Output 1 P34 P35 Comparator Output D0 P35...

Page 138: ...ree additional pins provide the Address Strobe Data Strobe and the Read Write Signal Figure 122 displays the Z8 CPU external interface pins Pin Descriptions The following sections briefly describe the...

Page 139: ...ata lines D7 D0 Port 0 1 mode registers must have bits D4 set equal to 1 and D3 set equal to 0 to con figure Port 1 as AD7 AD0 Inputs and outputs are TTL compatible See Figure 123 on page 133 Reset RE...

Page 140: ...t 0 1 Mode Reg ister F8h If bit 2 is set to 0 the stack is in external data memory see Figure 124 on page 134 The instruction used to change the stack selection bit should not be immediately followed...

Page 141: ...ta memory After a RESET DM is not selected Bus Operation Typical data transfers between Z8 CPU and external memory are displayed in Figure 126 on page 135 and Figure 127 on page 136 Machine cycles can...

Page 142: ...c timing relationship with other signals Figure 126 External Instruction Fetch or Memory Read Cycle Machine Cycle T1 T2 T3 Clock A15 A8 AD7 AD0 AS DS R W DM Read Cycle A8 A15 A7 A0 D7 D0 IN Port input...

Page 143: ...n stable throughout the machine cycle regardless of the addressing mode Data Strobe Z8 CPU uses DS to time the actual data transfer For Write operations R W Low a Low on DS indicates that valid data i...

Page 144: ...etches the DS timing by two clock periods Figure 128 and Figure 129 on page 138 display extended external memory Read and Write cycles Figure 128 Extended External Instruction Fetch or Memory Read Cyc...

Page 145: ...is due in part to the use of an instruction pipeline in which the instruction fetch and execution cycles are overlapped During the execution of Figure 129 Extended External Memory Write Cycle Figure 1...

Page 146: ...ed Figure 131 Instruction Cycle Timing 1 Byte Instructions Figure 132 Instruction Cycle Timing 2 and 3 Byte Instructions T1 T2 T3 T3 T1 DS AS R W T1 T2 T2 Fetch 1st Byte T3 M1 M2 M3 A15 A8 A15 A8 A15...

Page 147: ...Reset Conditions After a hardware reset extended timing is set to accommodate slow memory access dur ing the configuration routine DM is inactive the stack resides in the register file Port 0 1 and 2...

Page 148: ...g to each group and the number of operands required for each The source operand is src the destination operand is dst and a condition code is cc Table 26 Load Instructions Mnemonic Operands Instructio...

Page 149: ...Exclusive OR Table 29 Program Control Instructions Mnemonic Operands Instruction CALL dst Call Procedure DJNZ dst src Decrement and Jump Non Zero IRET Interrupt Return JP cc dst Jump JR cc dst Jump Re...

Page 150: ...struction RL dst Rotate Left RLC dst Rotate Left Through Carry RR dst Rotate Right RRC dst Rotate Right Through Carry SRA dst Shift Right Arithmetic SWAP dst Swap Nibbles Table 33 CPU Control Instruct...

Page 151: ...set or reset by instructions however only those instructions that do not affect the flags as an outcome of the execution should be used Load Immediate The Watchdog Timer WDT instruction affects the F...

Page 152: ...also 0 A negative number is identified by a 1 in the most significant bit position bit 7 therefore the Sign Flag is also 1 IRET changes the value of the Sign Flag when the Flag Register saved in the...

Page 153: ...f the Half Carry Flag when the Flag Register saved in the Stack is restored Condition Codes The C Z S and V Flags control the operation of the Conditional Jump instructions Six teen frequently useful...

Page 154: ...gs 0000 0 F Always False 1000 8 blank Always True 0111 7 C Carry C 1 1111 F NC No Carry C 0 0110 6 Z Zero Z 1 1110 E NZ Non Zero Z 0 1101 D PL Plus S 0 0101 5 Ml Minus S 1 0100 4 OV Overflow V 1 1100...

Page 155: ...Indirect Working Register Rn n 0 15 Irr Indirect Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect Register Pair Reg Reg represents an even number in the range 00h to FFh or Working Regis...

Page 156: ...ied in that order The following instruction descriptions show the format of the object code produced by the assembler This binary format should be followed if manual pro gram coding is preferred or if...

Page 157: ...register file range avail able The register file size varies by device type Z8 Instruction Summary Table 39 provides the summary of Z8 instruction set ASM ADD 43h 08h ADD dst src OBJ 04 08 43 OPC src...

Page 158: ...0 PC PC dst Range 127 128 r 0 F EI 9 F IMR 7 1 HALT 7 F INC dst dst dst 1 r rE r 0 F R 20 IR 21 INCW dst RR A0 dst dst 1 IR A1 Instruction and Operation Address Mode Op Code Byte Hex Flags Affected d...

Page 159: ...r 8 R r r 9 r 0 F r X C 7 X r D 7 r Ir E 3 Ir r F 3 R R E 4 R IR E 5 R IM E 6 IR IM E 7 IR R F 5 LDC dst src r Irr C 2 dst src lrr r D 2 LDCI dst src Ir Irr C 3 dst src r r 1 or rr rr 1 lrr Ir D 3 LD...

Page 160: ...70 SP SP 1 and SP src IR 71 RCF C 0 C F 0 RET PC SP SP SP 2 A F RL dst R IR 90 91 RLC dst R IR 10 11 RR dst R IR E 0 E 1 RRC dst R C 0 IR C 1 SBC dst src dst dst src C 3 1 SCF C 1 D F 1 SRA dst R D 0...

Page 161: ...modes which are encoded for brevity The first opcode nibble is found in the instruction set table above The second nibble is expressed symbolically by a in this table and its value is found in the fol...

Page 162: ...r Manual UM001604 0108 Instruction Set 155 Table 40 provides a summary of Z8 address modes Table 40 Summary of Z8 Address Modes Address Mode Lower Op Code Nibble dst src r r 2 r Ir 3 R R 4 R IR 5 R IM...

Page 163: ...0 5 LD IR1 IM 8 5 SWAP R1 8 5 SWAP IR1 6 5 LD Ir1 r2 10 5 LD R2 IR1 6 5 LD r1 R2 6 5 LD r2 R1 12 10 5 DJNZ r1 RA 12 10 0 JR cc RA 6 5 LD r1 IM 12 10 0 JP cc DA 6 5 INC r1 6 0 STOP 7 0 HALT 6 1 DI 6 1...

Page 164: ...crement Rotate Right Decrement and Jump if Non Zero Rotate Right Through Carry Decrement Word Set Carry Flag Disable Interrupts Set Register Pointer Enable Interrupts Shift Right Arithmetic Halt Rotat...

Page 165: ...king Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Cycles OPC Hex Address Mode dst src OPC dst src 6 02 r r 6 03 r lr OPC src dst 10 04 R R 10 0...

Page 166: ...ster R16 The C Z S V D and H Flags are all cleared Example 3 If Register 34h contains 2Eh and Register 12h contains 1Bh the statement ADD 34h 12h Op Code 04 12 34 leaves the value 49h in Register 34h...

Page 167: ...4 0108 Instruction Description 160 Example 6 If Register D4h contains 5Fh and Register 5Fh contains 4Ch the statement ADD D4h 02h Op Code 07 D4 02 leaves the value 4Eh in Register 5Fh The C Z S V D an...

Page 168: ...tination Working Register operand is specified by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destinatio...

Page 169: ...S V D and H Flags are all cleared Example 3 If Register 34h contains 2Eh the C Flag is set and Register 12h contains 1Bh the state ment ADC 34h 12h Op Code 14 12 34 leaves the value 4Ah in Register 3...

Page 170: ...struction Description 163 Example 6 If Register D4h contains 5Fh Register 5Fh contains 4Ch and the C Flag is set the state ment ADC D4h 02h Op Code 17 D4 02 leaves the value 4Fh in Register 5Fh The C...

Page 171: ...e procedure a RET return instruction can be used to return to the original program flow RET pops the top of the Stack and replace the original value into the PC Address mode IRR can be used to specify...

Page 172: ...be loaded with 3521h The PC now points to the address of the first statement in the procedure to be executed Example 2 If the contents of the PC are 1A47h the contents of the SP Register FFh are 72h...

Page 173: ...C NOT C The C Flag is complemented If C 1 then it is changed to C 0 or if C 0 then it is changed to C 1 Example If the C Flag contains a 0 the statement CCF Op Code EF changes the C Flag from C 0 to C...

Page 174: ...example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Example If Working Register R6 contains AFh the statement CLR R6 Op Code B0 E6...

Page 175: ...ed by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Example 1 If Regist...

Page 176: ...uction Description 169 Example 2 If Register 08h contains 24h and Register 24h contains FFh 11111111b the state ment COM 08h Op Code 61 08 leaves the value 00h 00000000b in Register 24h The Z Flag is...

Page 177: ...ing 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Example 1 Cycles OPC Hex Add...

Page 178: ...Register 34h contains 2Eh and Register 12h contains 1Bh the statement CP 34h 12h Op Code A4 12 34 clears the C Z S and V Flags Example 4 If Register 4Bh contains 82h Working Register R3 contains 10h...

Page 179: ...e operation performed If the destination operand is not the result of a valid addition or subtraction of BCD digits the operation is undefined Cycles OPC Hex Address Mode dst OPC dst 8 40 R 8 41 IR In...

Page 180: ...0010 0111 27h 0011 1100 3Ch If the result of the addition is stored in Register 5Fh the statement DA 5Fh Op Code 40 5F adjusts this result so the correct BCD representation is obtained 0011 1100 3Ch 0...

Page 181: ...value 5Fh and the result of the addition is stored in Register 5Fh the statement DA 45h Op Code 40 45 adjusts this result so the correct BCD representation is obtained 0011 1100 3Ch 0000 0110 06h 0100...

Page 182: ...estination operand in the Op Code Example 1 If Working Register R10 contains 2A the statement DEC R10 Op Code 00 EA leaves the value 29h in Working Register R10 The Z V and S Flags are cleared Example...

Page 183: ...JNZ statement When the specified Working Register counter reaches zero control falls through to the statement following the DJNZ instruction The Working Register being used as a counter must be one of...

Page 184: ...nstruction Description 177 End the loop with DJNZ The assembly listing required for this routine is as follows LD R6 12 Load Counter LOOP LD R9 R6 Move one byte to LD R6 R9 new location DJNZ R6 LOOP D...

Page 185: ...ple if Working Register Pair R12 CH is the des tination operand then ECh is used as the destination operand in the Op Code Example 1 If Register Pair 30h and 31h contain the value 0AF2h the statement...

Page 186: ...Z8 CPU User Manual UM001604 0108 Instruction Description 179 DECW R0 Op Code 81 E0 leaves the value FAF2h in Register Pair 30h and 31h The S Flag is set and the Z and V Flags are cleared...

Page 187: ...ey remain potentially enabled For example the Global Interrupt Enable is cleared but not the individual interrupt level enables Example If Control Register FBh contains 8Ah 10001010 interrupts IRQ1 an...

Page 188: ...is set to 1 This allows poten tially enabled interrupts to become enabled Example If Control Register FBh contains 0Ah 00001010 interrupts IRQ1 and IRQ3 are selected the statement EI Op Code 9F sets...

Page 189: ...upts either externally or internally generated In order to enter HALT mode it is necessary to first flush the instruction pipeline to avoid suspending execution in mid instruction You must execute a N...

Page 190: ...destination operand in the Op Code Example 1 If Working Register R10 contains 2Ah the statement INC R10 Op Code AE leaves the value 2Bh in Working Register R10 The Z V and S Flags are cleared Example...

Page 191: ...0108 Instruction Description 184 Example 3 If Register B3h contains CBh and Register BCh contains FFh the statement INC B3h Op Code 21 B3 leaves the value 00h in Register CBh The Z Flag is set and th...

Page 192: ...g 1110b Eh to the high nibble of the operand For example if Working Register Pair R12 CH is the des tination operand then ECh is used as the destination operand in the Op Code Example 1 If Register Pa...

Page 193: ...ption 186 Example 2 If Working Register R0 contains 30h and Register Pairs 30h and 31h contain the value FAF3h the statement INCW R0 Op Code A1 E0 leaves the value FAF4h in Register Pair 30h and 31h T...

Page 194: ...ains 6Fh and Register 47 contains E4h the statement IRET Op Code BF restores the FLAG Register FCh with the value 00h restores the PC with the value 6FE4h re enables the interrupts and sets the Stack...

Page 195: ...pair specified by the destination operand Program Control then passes to the instruction addressed by the PC Address mode IRR can be used to specify a 4 bit Working Register In this format the desti n...

Page 196: ...control to that location If the Carry Flag had not been set control would have fallen through to the statement following the JP instruction Example 2 If Working Register Pair RR2 contains the value 3F...

Page 197: ...PC is taken to be the address of the first instruction byte following the JR instruction Example 1 If the result of the last arithmetic operation executed is negative the next four statements which oc...

Page 198: ...nts of the source operand are not affected Cycles OPC Hex Address Mode dst src dst OPC src 6 rC r IM 6 r8 r R src OPC dst 6 r9 R r r 0 to F OPC dst OPC 6 E3 r Ir 6 F3 Ir r OPC src dst 10 E4 R R 10 E5...

Page 199: ...e statement LD R14 34h Op Code F8 34 loads the value FCh into Working Register R15 The contents of Register 34h are not affected Example 3 If Working Register R14 contains the value 45h the statement...

Page 200: ...e ment LD 34h 45h Op Code E5 45 34 loads the value FFh into Register 34h The contents of Register 45h and Register CFh are not affected Example 8 The statement LD 34h A4h Op Code E6 34 A4 loads the va...

Page 201: ...he value 4Fh The contents of Working Register R0 and Register 2Ch are not affected Example 12 If Working Register R0 contains the value 0Bh and Working Register R10 contains 83h the statement LD F0h R...

Page 202: ...Register Pair R6 and R7 contain the value 30A2h and Program Memory loca tion 30A2h contains the value 22h the statement LDC R2 RR6 Op Code C2 26 loads the value 22h into Working Register R2 The value...

Page 203: ...nstruction Description 196 loads the value 22h into Program Memory location 10A2h The value of Working Regis ter R2 is unchanged by the load This instruction format is valid only for MCUs which can ad...

Page 204: ...destination location Both addresses in the Working Registers are then incremented automatically The contents of the source operand are not affected Example 1 If Working Register Pair R6 R7 contains 30...

Page 205: ...r 20h contains 22h Register 21h contains BCh and Working Register Pair R6 R7 contains 30A2h the statement LDCI RR6 R2 Op Code D3 26 loads the value 22h into Program Memory location 30A2h Working Regis...

Page 206: ...egister Pair R6 and R7 contain the value 40A2h and external data memory location 40A2h contains the value 22h the statement LDE R2 RR6 Op Code 82 26 loads the value 22h into Working Register R2 The va...

Page 207: ...User Manual UM001604 0108 Instruction Description 200 loads the value 22h into external data memory location 404Ah This instruction format is valid only for MCUs which can address external data memor...

Page 208: ...nto the destination location Both addresses in the Working Registers are then incremented automatically The contents of the source are not affected Example 1 If Working Register Pair R6 and R7 contain...

Page 209: ...rking Register Pair R6 and R7 contains 404Ah the statement LDEI RR6 R2 Op Code 93 26 loads the value ABh into external data memory location 404Ah Working Register R2 is incremented to 23h and Working...

Page 210: ...ion Syntax NOP Instruction Format Operation No action is performed by this instruction It is typically used for timing delays or clearing the pipeline Cycles OPC Hex OPC 6 FF Flag Description C Unaffe...

Page 211: ...s R or IR can be used to specify a 4 bit Working Register In this format the source or destination Working Register operand is specified by adding 1110b Eh to the high nibble of the operand For exampl...

Page 212: ...3Ah contains the value F5h 11110101b and Register 42h contains the value 0Ah 00001010 the statement AND 3Ah 42h Op Code 54 42 3A leaves the value 00h 00000000b in Register 3Ah The Z Flag is set and th...

Page 213: ...Description 206 Example 6 If Working Register R3 contains the value 3Eh and Register 3Eh contains the value ECh 11101100b the statement AND R3 05h Op Code 57 E3 05 leaves the value 04h 00000100b in R...

Page 214: ...Address modes R or IR can be used to specify a 4 bit Working Register In this format the source or destination Working Register operand is specified by adding 1110b Eh to the high nibble of the operan...

Page 215: ...is set and the Z and V Flags are cleared Example 3 If Register 3Ah contains the value F5h 11110101b and Register 42h contains the value 0Ah 00001010 the statement OR 3Ah 42h Op Code 44 42 3A leaves th...

Page 216: ...n Description 209 Example 6 If Working Register R3 contains the value 3Eh and Register 3Eh contains the value 0Ch 00001100b the statement OR R3 05h Op Code 57 E3 05 leaves the value 0Dh 00001101b in R...

Page 217: ...ddress modes R or IR can be used to specify a 4 bit Working Register In this format the source or destination Working Register operand is specified by adding 1110b Eh to the high nibble of the operand...

Page 218: ...is set and the Z and V Flags are cleared Example 3 If Register 3Ah contains the value F5h 11110101b and Register 42h contains the value 0Ah 00001010b the statement XOR 3Ah 42h Op Code B4 42 3A leaves...

Page 219: ...Description 212 Example 6 If Working Register R3 contains the value 3Eh and Register 3Eh contains the value 6Ch 01101100b the statement XOR R3 05h Op Code B7 E3 05 leaves the value 69h 01101001b in R...

Page 220: ...by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Example 1 If the SP Co...

Page 221: ...s FEh and FFh contains the value 1000h external data mem ory location 1000h contains 55h and Working Register R6 contains 22h the statement POP R6 Op Code 51 E6 loads the value 55h into Register 22h A...

Page 222: ...ing Register operand is specified by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in...

Page 223: ...ion Description 216 Example 2 If the SP contains 61h and Working Register R4 contains FCh the statement PUSH R4 Op Code 71 E4 stores the contents of Register FCh the Flag Register in location 60h Afte...

Page 224: ...ion Format Operation C 0 The C Flag is reset to 0 regardless of its previous value Example If the C Flag is currently set the statement RCF Op Code CF resets the Carry Flag to 0 Cycles OPC Hex OPC 6 C...

Page 225: ...cuted within the subroutine should be countered with a POP instruction in order to guarantee the SP is at the correct location when the RET instruction is executed Otherwise the wrong address is loade...

Page 226: ...s modes R or IR can be used to specify a 4 bit Working Register In this format the destination Working Register operand is specified by adding 1110b Eh to the high nibble Cycles OPC Hex Address Mode d...

Page 227: ...of Register C6h are 88h 10001000b the statement RL C6h Op Code 80 C6 leaves the value 11h 00010001b in Register C6h The C and V Flags are set and the S and Z Flags are cleared Example 2 If the conten...

Page 228: ...0 as shown below Address modes R or IR can be used to specify a 4 bit Working Register In this format the destination Working Register operand is specified by adding 1110b Eh to the high nibble Cycle...

Page 229: ...et and Register C6 contains 8Fh 10001111b the statement RLC C6 Op Code 10 C6 leaves Register C6 with the value 1Eh 00011110b The C and V Flags are set and S and Z Flags are cleared Example 2 If the C...

Page 230: ...rmat the destination Working Register operand is specified by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as th...

Page 231: ...R6 Op Code E0 E6 leaves the value 98h 10011000 in Working Register R6 The C V and S Flags are set and the Z Flag is cleared Example 2 If the contents of Register C6 are 31h and the contents of Regist...

Page 232: ...s shown below Address modes R or IR can be used to specify a 4 bit Working Register In this format the destination Working Register operand is specified by adding 1110b Eh to the high nibble Cycles OP...

Page 233: ...ister C6h are DDh 11011101b and the C Flag is reset the state ment RRC C6h Op Code C0 C6 leaves the value 6Eh 01101110b in register C6h The C and V Flags are set and the Z and S Flags are cleared Exam...

Page 234: ...tion Format Operation C 1 The C Flag is set to 1 regardless of its previous value Example If the C Flag is currently reset the statement SCF Op Code DF sets the Carry Flag to 1 Cycles OPC Hex OPC 6 DF...

Page 235: ...ster Group while using Expanded Register Banks points to Bank 0 Example 1 SRP TD addresses Working Register Group 7 of Bank 0 Cycles OPC Hex Address Mode dst OPC src 6 31 IM Register Pointer FDh Worki...

Page 236: ...ts the Register Pointer to access expanded Register Bank 0 and Working Register Group F in the Z8 Standard Register File All references to Working Registers now affect this Register Pointer FDh Conten...

Page 237: ...Registers now affect this group of 16 registers These registers are now accessed as Working Registers R0 to R15 Port Reg isters are now not accessable Example 4 Assume the RP currently addresses the...

Page 238: ...anged and its value is shifted into bit 6 as shown below Address modes R or IR can be used to specify a 4 bit Working Register In this format des tination Working Register operand is specified by addi...

Page 239: ...s of Working Register R6 are 31h 00110001B the statement SRA R6 Op Code D0 E6 leaves the value 98h 00011000 in Working Register R6 The C Flag is set and the Z V and S Flags are cleared Example 2 If Re...

Page 240: ...the processor to restart the application program at address 000Ch In order to enter STOP mode it is necessary to first flush the instruction pipeline to avoid suspending execution in mid instruction...

Page 241: ...r example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Cycles OPC Hex Address Mode dst src OPC dst src 6 22 r r 6 23 r lr OPC src ds...

Page 242: ...R15 The D Flag is set and the C Z S V and H Flags are cleared Example 3 If Register 34h contains 2Eh and Register 12h contains 1Bh the statement SUB 34h 12h Op Code 24 12 34 leaves the value 13h in Re...

Page 243: ...Instruction Description 236 Example 6 If Register D4h contains 5Fh Register 5Fh contains 4Ch the statement SUB D4h 02h Op Code 17 D4 02 leaves the value 4Ah in Register 5Fh The D Flag is set and the...

Page 244: ...at the source or destination Working Register operand is specified by adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is us...

Page 245: ...he value 05h in Working Register R15 The D Flag is set and the C Z S V and H Flags are cleared Example 3 If Register 34h contains 2Eh the C Flag is set and Register 12h contains 1Bh the state ment SBC...

Page 246: ...er 6Ch The D Flag is set and the C Z S V and H Flags are cleared Example 6 If Register D4h contains 5Fh Register 5Fh contains 4Ch and the C Flag is set the state ment SBC D4h 02h Op Code 37 D4 02 leav...

Page 247: ...adding 1110b Eh to the high nibble of the operand For example if Working Register R12 CH is the destination operand then ECh is used as the destination operand in the Op Code Example 1 If Register BCh...

Page 248: ...08 Instruction Description 241 Example 2 If Working Register R5 contains BCh and Register BCh contains B3h 10110011B the statement SWAP R5h Op Code F1 E5 leaves the value 3Bh 00111011B in Register BCh...

Page 249: ...its were 1 When the TCM operation is complete the destination and source operands still contain their original values Address modes R or IR can be used to specify a 4 bit Working Register In this form...

Page 250: ...is not a 1 The V and S Flags are also cleared Example 3 If Register D4h contains the value 04h 000001000b and Working Register R0 contains the value 80h 10000000b bit 7 is being tested if it is 1 the...

Page 251: ...bit 1 in the destina tion operand was 1 The S and V Flags are cleared Example 6 If Register 5Dh contains A0h and Register A0h contains 0Fh 00001111b the state ment TCM 5D 10h Op Code 67 5D 10 tests b...

Page 252: ...TM operation is complete the destina tion and source operands still contain their original values Address modes R or IR can be used to specify a 4 bit Working Register In this format the source or de...

Page 253: ...d is not a 0 The S Flag is set and the V Flag is cleared Example 3 If Register D4h contains the value 08h 00001000b and Working Register R0 contains the value 04h 00000100b bit 2 is being tested if it...

Page 254: ...ing bit 1 in the destina tion operand was 0 The S and V Flags are cleared Example 6 If Register 5Dh contains A0h and Register A0h contains 0Fh 00001111b the state ment TM 5D 10h Op Code 77 5D 10 tests...

Page 255: ...on of the WDT instruction refreshes the timer and prevents the WDT from timing out The WDT instruction should not be used following any instruction in which the condition of the Flags is important Exa...

Page 256: ...s it possible to have the WDT function running during HALT mode A WDh instruction executed without executing WDT 5Fh has no effect The WDh instruction should not be used following any instruction in w...

Page 257: ...ster 115 H HALT 110 HALT and STOP 110 Halt Mode Operation 110 I Initialization 99 Input 115 Instruction Timing 138 Interface 131 interrupt acknowledge time 107 Interrupt Cycle 107 Interrupt Generation...

Page 258: ...126 Receiver Operation 118 Receiver Shift Register 118 Recovery 112 Recovery Register 112 Register File 104 Reset 109 Reset Conditions 109 RUN 110 RUN mode 110 S SCON 123 Serial 115 Serial Input Outp...

Page 259: ...Z8 CPU User Manual UM001604 0108 Index 252 V Vectored 105 Vectored Interrupt Cycle Timing 107 Vectored Processing 105 W Worst Case 107 Z Z8 140 Z8 Reset Conditions 140...

Page 260: ...technical questions about the product documentation or any other issues with Zilog s offerings please visit Zilog s Knowledge Base at http www zilog com kb For any comments detail technical questions...

Page 261: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information ZiLOG Z86E3412SEG...

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