ZiLOG Z8 CPU, User Manual

Page: 94 / 261

Z8
®
CPU
User Manual
UM001604-0108 Counters and Timers
87
and bit 6 to 1 and 0, respectively. The counter/timer T
OUT
mode is turned off by setting
TMR bit and bit 6 both to 0, freeing P36 to be a data output line.
T
OUT
is initialized to a logic 1 whenever the TMR Load bit (bit 0 for T0 or bit 1 for T2) is
set to 1. The T
OUT
configuration timer load, and Timer Enable Count bits for the counter/
timer driving the T
OUT
pin can be set at the same time. For example, using the instruction:
OR TMR,#43h
•
Configures T0 to drive the T
OUT
pin (P36)
•
Sets the P36 T
OUT
pin to a logic 1 level
•
Loads the initial PRE0 and T0 levels into their respective counters and starts the
counter after the M2T2 machine state after the operand is fetched
At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a toggle flip-flop. The
output of this flip-flop drives the T
OUT
line, P36. In all cases, when the selected counter/
timer reaches its end-of-count, T
OUT
toggles to its opposite state (see Figure 78 ). If, for
example, the counter/timer is in CONTINUOUS COUNTING Mode, Tout has a 50 per-
cent duty cycle output. This duty cycle can easily be controlled by varying the initial val-
ues after each end-of-count.
The internal clock can be selected as output instead of T0 or T1 by setting TMR bit 7 and
bit 6 both to 1. The internal clock (XTAL frequency ÷ 2) is then directly output on P36
(see
Figure 79 on page 88).
While programmed as T
OUT
, P36 cannot be modified by a write to port register P3. How-
ever, the Z8
®
software can examine the P36 current output by reading the port register.
Figure 78. T0 and T1 Output Through T
OUT
÷
2 P36
T
OUT
TMR
D7–D6 = 01
IRQ
4
(T0 End-of-Count)
IRQ
5
(T1 End-of-Count)
TMR
D7–D6 = 10