Z8
®
CPU
User Manual
UM001604-0108
Instruction Set
144
Processor Flags
The Flag Register
(FCh)
informs about the current status of Z8
®
CPU. The flags and their
bit positions in the Flag Register are displayed in
.
Z8 Flag Register contains six bits of status information which are set or cleared by CPU
operations. Four of the bits (C, V, Z, and S) can be tested for use with conditional Jump
instructions. Two flags (H and D) cannot be tested and are used for BCD arithmetic. The
two remaining bits in the Flag Register (F1 and F2) are available, but they must be set or
cleared by instructions and are not usable with conditional Jumps.
As with bits in the other control registers, the Flag Register bits can be set or reset by
instructions; however, only those instructions that do not affect the flags as an outcome of
the execution should be used (Load Immediate).
The Watchdog Timer (WDT) instruction affects the Flags accordingly: Z = 1, S = 0, V = 0.
Carry Flag
The Carry Flag (C) is set to 1 whenever the result of an arithmetic operation generates a
carry or a borrow the high order bit 7. Otherwise, the Carry Flag is cleared to 0.
Following Rotate and Shift instructions, the Carry Flag contains the last value shifted out
of the specified register.
An instruction can set, reset, or complement the Carry Flag.
IRET may change the value of the Carry Flag when the Flag Register, saved in the Stack,
is restored.
Figure 133. Z8 Flag Register
Note:
D7 D6 D5 D4 D3 D2 D1 D0
Flag Register (Read/Write)
Half Carry Flag (H)
User Flag (F1)
User Flag (F2)
Register FCh (Flags)
Overflow Flag (V)
Carry Flag (C)
Decimal Adjust Flag (D)
Zero Flag (Z)
Sign Flag (S)
