ZiLOG Z8 CPU, User Manual

Page: 31 / 261

Z8
®
CPU
User Manual
UM001604-0108 Clock
24
Clock
Z8
®
CPU derives its timing from on-board clock circuitry connected to pins XTAL1 and
XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and
a clock buffer.
Figure 12 displays the clock circuitry. The oscillator’s input is XTAL1 and
its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock,
RC, or an external clock source.
Frequency Control
In some cases, the Z8 CPU has an EPROM/OTP option or a Mask ROM option bit to
bypass the divide-by-two flip flop in
Figure 12 . This feature is used in conjunction with
the low EMI option. When low EMI is selected, the device output drive and oscillator
drive is reduced to approximately 25 percent of the standard drive and the divide-by-two
flip flop is bypassed such that the XTAL clock frequency is equal to the internal system
clock frequency. In this mode, the maximum frequency of the XTAL clock is 4 MHz.
Refer to specific product specification for availability of options and output drive charac-
teristics.
Clock Control
In some cases, the Z8 CPU offers software control of the internal system clock via pro-
gramming register bits. The bits are located in the Stop Mode Recovery Register in
Expanded Register File Bank F, Register
0Bh
. This register selects the clock divide value
and determines the mode of Stop Mode Recovery (see Figure 13 on page 25). Refer to the
specific product specification for availability of this feature/register.
Figure 12. Z8
®
CPU Clock Circuit
÷
2
OSC
XTAL2
Internal
Buffer
XTAL1
Clock