Z-World OP7100, User Manual

Page: 48 / 122

OP7100 48 s Hardware
Prescaler
(
PS
)
÷10
or
÷30
Processor
Clock
Divider
1
2
...
64
Divide
Ratio
(
DR
)
16
or
64
External
Clock
The prescaler (PS), the divide ratio (DR), and the SS bits form a baud-rate
generator, as shown in Figure 3-22.
Figure 3-22. Z180 Baud-Rate Generator
DR (Divide Ratio)
This bit controls one stage of frequency division in the baud-rate generator.
If 1 then divide by 64. If 0 then divide by 16. This is the only control bit
that affects the external clock frequency.
PEO (Parity Even/Odd)
This bit affects parity: 0 Þ even parity, 1 Þ odd parity. It is effective only
if MOD1 is set in CNTLA (parity enabled).
/CTS/PS (Clear to Send/Prescaler)
When read, this bit gives the state of external pin
/CTS
: 0 Þ low,
1 Þ high. When
/CTS
is high, RDRF is inhibited so that incoming receive
characters are ignored. When written, this bit has an entirely different
function. If a 0 is written, the baud-rate prescaler is set to divide by 10. If a
1 is written, it is set to divide by 30.
MP (Multiprocessor Mode)
When this bit is set to 1, the multiprocessor mode is enabled. The multi-
processor bit (MPB) is included in transmitted data as shown here.
start bit, data bits, MPB, stop bits
The MPB is 1 when MPBT is 1 and 0 when MPBT is 0.
MPBT (Multiprocessor Bit Transmit)
This bit controls the multiprocessor bit (MPB). When MPB is 1, transmit-
ted bytes will get the attention of other units listening only for bytes with
MPB set.