Z-World OP7100, User Manual

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OP7100 44 s Hardware
Asynchronous Serial Communication Interface
The Z180 incorporates an asynchronous serial communication interface
(ACSI) that supports two independent full-duplex channels.
ASCI Status Registers
A status register for each channel provides information about the state of
each channel and allows interrupts to be enabled and disabled.
STAT0
(04H)
7 6 5 4 3 2 1 0
RDRF OVRN PE FE RIE /DCD0 TDRE TIE
R R R R R / W R R R / W
STAT1
(05H)
7 6 5 4 3 2 1 0
RDRF OVRN PE FE RIE CTS1E TDRE TIE
R R R R R / W R R R / W
/DCD0 (Data Carrier Detect)
This bit echoes the state of the
/DCD0
input pin for Channel 0. However,
when the input to the pin switches from high to low, the data bit switches
low only after STAT0 has been read. The receiver is held to reset as long
as the input pin is held high. This function is not generally useful because
an interrupt is requested as long as
/DCD0
is a 1. This forces the program-
mer to disable the receiver interrupts to avoid endless interrupts. A better
design would cause an interrupt only when the state of the pin changes.
This pin is tied to ground in the CM7000.
TIE (Transmitter Interrupt Enable)
This bit masks the transmitter interrupt. If set to 1, an interrupt is requested
whenever TDRE is 1. The interrupt is not edge-triggered. Set this bit to 0
to stop sending. Otherwise, interrupts will be requested continuously as
soon as the transmitter data register is empty.
TDRE (Transmitter Data Register Empty)
A 1 means that the channel is ready to accept another character. A high
level on the
/CTS
pin forces this bit to 0 even though the transmitter is
ready.