Yamaha HTR-6230, Service Manual

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RX-V365/HTR-6230
RX-V365/HTR-6230
Pin No. Function Name I/O Detail of Function
1 INT1 O Interrupt 1 pin
2 BOUT O Block-start output pin for receiver input “H” during first 40 flames
3 TVDD – Output buffer power supply pin, 2.7 V to 5.5 V
4 DVDD – Digital power supply pin, 4.5 V to 5.5 V
5 DVSS – Digital ground pin
6 XTO O X’tal clock output pin
7 XTI I X’tal / External clock input pin
8 TEST3 I
Test 3 pin
This pin should be connected to DVSS
9 MCKO2 O Master clock output 2 pin
10 MCKO1 O Master clock output 1 pin
11 COUT O C-bit output pin for receiver input
12 UOUT O U-bit output pin for receiver input
13 VOUT O V-bit output pin for receiver input
14 SDTO2 O Audio serial data output pin (DIR/DIT part)
15 BICK2 I/O Audio serial data clock pin (DIR/DIT part)
16 LRCK2 I/O Channel clock pin (DIR/DIT part)
17 SDTO1 O Audio serial data output pin (ADC/DAC part)
18 BICK1 I/O Audio serial data clock pin (ADC/DAC part)
19 LRCK1 I/O Input channel clock pin
20 CDTO O Control data output pin in serial mode, I2C pin= “L”
21
CCLK I Control data clock pin in serial mode, I2C pin= “L”
SCL I Control data clock pin in serial mode, I2C pin= “H”
22
CDTI I Control data input pin in serial mode, I2C pin= “L”
SDA I/O Control data pin in serial mode, I2C pin= “H”
23 CSN
I Chip select pin in serial mode, I2C pin=”L”
I This pin should be connected to DVSS, I2C pin=”H”
24 DAUX1 I AUX audio serial data input pin (ADC/DAC part)
25 SDTI4 I DAC4 audio serial data input pin
26 SDTI3 I DAC3 audio serial data input pin
27 SDTI2 I DAC2 audio serial data input pin
28 SDTI1 I DAC1 audio serial data input pin
29 XTL1 I X’tal frequency select 0 pin
30 XTL0 I X’tal frequency select 1 pin
31 PDN I
Power-down mode pin
When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are reset
When CAD1-0 pins are changed, the AK4588 should be reset by PDN pin
32 MASTER I
Master mode select pin
“H”: Master mode, “L”: Slave mode
33
DZF2 O
Zero input detect 2 pin (table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin
goes to “H” / When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”
OVF O
Analog input overflow detect pin
This pin goes to “H” if the analog input of L ch or R ch overflows
This pin becomes OVF pin if OVFE bit is set to 1
34 DZF1 O
Zero input detect 1 pin (table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin
goes to “H” / When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”
35 LOUT4 O DAC4 L ch analog output pin
36 NC –
No connect pin
No internal bonding / This pin should be opened
37 ROUT4 O DAC4 R ch analog output pin
38 NC –
No connect pin
No internal bonding / This pin should be opened
39 LOUT3 O DAC3 L ch analog output pin
40 NC –
No connect pin
No internal bonding / This pin should be opened