Yamaha HTR-6230, Service Manual

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RX-V365/HTR-6230
RX-V365/HTR-6230
Pin No. Function Name I/O Detail of Function
41 ROUT3 O DAC3 R ch analog output pin
42 NC –
No connect pin
No internal bonding / This pin should be opened
43 LOUT2 O DAC2 L ch analog output pin
44 NC –
No connect pin
No internal bonding / This pin should be opened
45 ROUT2 O DAC2 R ch analog output pin
46 NC –
No connect pin
No internal bonding / This pin should be opened
47 LOUT1 O DAC1 L ch analog output pin
48 NC –
No connect pin
No internal bonding / This pin should be opened
49 ROUT1 O DAC1 R ch analog output pin
50 NC – No connect pin
No internal bonding / This pin should be opened
51 LIN I L ch analog input pin
52 RIN I R ch analog input pin
53 VCOM –
Common voltage output pin
2.2 F capacitor should be connected to AVSS externally
54 VREFH – Positive voltage reference input pin, AVDD
55 AVDD – Analog power supply pin, 4.5 V to 4.5 V
56 AVSS – Analog ground pin, 0 V
57 RX0 I Receiver channel 0 pin (Internal biased pin / Internally biased at PVDD/2)
58 NC –
No connect pin
No internal bonding / This pin should be connected to PVSS
59 RX1 I Receiver channel 1 pin (Internal biased pin / Internally biased at PVDD/2)
60 TEST1 I
Test 1 pin
This pin should be connected to PVSS
61 RX2 I Receiver channel 2 pin (Internal biased pin / Internally biased at PVDD/2)
62 NC –
No connect pin
No internal bonding / This pin should be connected to PVSS
63 RX3 I Receiver channel 3 pin (Internal biased pin / Internally biased at PVDD/2)
64 PVSS – PLL ground pin
65 R –
External resistor pin
12 k-ohms +/-1 % resistor should be connected to PVSS externally
66 PVDD – PLL power supply pin, 4.5 V to 4.5 V
67 RX4 I Receiver channel 4 pin (Internal biased pin / Internally biased at PVDD/2)
68 TEST2 I
Test 2 pin
This pin should be connected to PVSS
69 RX5 I Receiver channel 5 pin (Internal biased pin / Internally biased at PVDD/2)
70 CAD0 I Chip address 0 pin (ADC/DAC part)
71 RX6 I Receiver channel 6 pin (Internal biased pin / Internally biased at PVDD/2)
72 CAD1 I Chip address 1 pin (ADC/DAC part)
73 RX7 I Receiver channel 7 pin (Internal biased pin / Internally biased at PVDD/2)
74 I2C I
Control mode select pin
“L”: 4-wire serial, “H”: I2C bus
75 DAUX2 I Auxiliary audio data input pin (DIR/DIT part)
76 VIN I V-bit input pin for transmitter output
77 MCLK I Master clock input pin
78 TX0 O Transmit channel (through data) output 0 pin
79 TX1 O
Transmit channel output 1 pin
When TX bit = “0”, transmit channel (through data) output 1 pin.
When TX bit = “1”, transmit channel (DAUX2 data) output pin (default)
80 INT0 O Interrupt 0 pin
Note: All input pins except internal biased pins and internal pull-down pin should not be left floating.