USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
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XSYS Interface [G]
A standard XMOS XSYS interface is provided to allow host debug of the board via
JTAG.
An XTAG2 USB debug adapter can be plugged into this port to allow running/debug-
ging code, programming the FLASH memory and selection of boot mode. A 20-way
IDC header is used as the physical connector and the pinout of this is shown below:
Signal
Pin
Description
TRST_N
3
JTAG Test Reset. Active low.
TMS
7
JTAG Test Mode Select.
TCK
9
JTAG Test Clock.
TD1
5
JTAG Test Data. From debug adapter to XS1-L1.
TD2
13
JTAG Test Data. From XS1-L1 to debug adapter.
SRST_N
15
System Reset. Active low. Resets XS1-L1 device.
DEBUG
11
XS1-L1 DEBUG Interrupt line.
GND
4, 8, 12, 16, 20
Ground.
NC
1, 2, 6, 10, 14, 17, 18, 19
These pins are not connected.
On power on, the XS1-L1 boots from the on-board flash memory. With the XTAG2
connected, the XS1-L1 can be reset and then booted from a program on the host PC.
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