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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)

7/18

5

Optical digital output [D]

An optical digital audio transmitter is used to provide a digital audio output in

IEC60958 consumer mode (S/PDIF) format. The S/PDIF signal is generated from a

1-bit port on the processor as defined in the port map. The data stream from the L1

is reclocked using the external master clock to synchronise the data into the audio
clock domain. This is achieved using a simple external D-type flip-flop.

6

SPI Flash Memory [F]

The board contains a 1Mbit FLASH memory device which is connected via a standard

Serial Peripheral Interface (SPI).

The FLASH is connected to four 1-bit ports as shown in the port map. These are the

standard ports the processor will try to boot from in boot from SPI mode.

Three of these ports are shared with I

2

S digital audio signals therefore the FLASH

cannot be accessed at the same time as digital audio is playing. When accessing the
SPI FLASH, the CODEC is held in reset and it ignores the three inputs shared with SPI
signals. When digital audio is playing, the FLASH is deselected by holding its chip
select (slave select) line inactive. In this mode, the FLASH will ignore other input
signals and set its output high impedance therefore it does not affect the shared
signals. The slave select signal is only active when booting the device therefore and
is held inactive while audio is playing.

The XMOS development tools include the XFLASH utility for programming compiled

programs into the flash memory. Software may also access the FLASH memory at
run-time by interfacing with the above ports. Note that, as mentioned, this can not
happen simultaneously with audio IO.

www.xmos.com

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Summary of Contents for XS1-L1

Page 1: ...Audio 2 0 Reference Design XS1 L1 Edition Hardware Manual Version 1 0 Publication Date 2009 10 05 Copyright 2009 XMOS Ltd All Rights Reserved Downloaded from Elcodis com electronic components distribu...

Page 2: ...1 2896MHz Passive LPF Passive LPF 3 5mm Stereo TRS Jack 3 5mm Stereo TRS Jack Optical Digital Audio Transmitter USB High Speed 480Mb s ULPI 5V VBus CODEC Analogue Supply L1 Core Supply 3V3D I2S Analog...

Page 3: ...ches and two LEDs for programmable use The diagram below shows the layout of the main components on the board H B M N B J L I I K C F E E D H G A A XS1 L1 Device H Push Button Switch B USB Connector T...

Page 4: ...o 30 75 This results in a core clock frequency of 399 75MHz and an I O reference clock frequency of 99 9375MHz 2 2 Reset A supply voltage supervisor connected to the 1V0 core supply is used to provide...

Page 5: ...t no serial configuration interface is required The digital audio interface is set to I2 S mode with all clocks being inputs slave mode The CODEC has three internal modes depending on the sampling rat...

Page 6: ...displayed below OUT IN A simple passive ac coupling and low pass filter circuit is used on input and output The circuit is configured so that the audio output will produce approximately 1VRMS 0dBV fo...

Page 7: ...I mode Three of these ports are shared with I2 S digital audio signals therefore the FLASH cannot be accessed at the same time as digital audio is playing When accessing the SPI FLASH the CODEC is hel...

Page 8: ...w Signal Pin Description TRST_N 3 JTAG Test Reset Active low TMS 7 JTAG Test Mode Select TCK 9 JTAG Test Clock TD1 5 JTAG Test Data From debug adapter to XS1 L1 TD2 13 JTAG Test Data From XS1 L1 to de...

Page 9: ...re connected to two 1 bit ports the mapping of which can be seen in the port map The port will go logic low when the button is pressed 9 User LEDs I The board provides two user LEDs that can be driven...

Page 10: ...ed by the USB3318 USB transceiver A low noise LDO regulator is used to generate the analogue supply for the Audio CODEC The CODEC offers higher audio performance at higher supply voltages so the volta...

Page 11: ...r standard canned oscillators could also be used The oscillator design is a simple Pierce oscillator using an unbuffered inverter as the amplifying component The MCLK_SEL signal selects which of the t...

Page 12: ...DEC_SCLK 4 P1C0 SPI_CLK CODEC_LRCK 5 NA CODEC_MCLK 6 P32A2 MCLK_SEL 7 P32A1 CODEC_RST_N 8 NA GND 9 P1L0 SPDIF_TX 10 NA SPDIF_OUT 11 P32A6 XD55 12 P32A7 XD56 13 P32A8 XD57 14 P32A9 XD58 15 P32A10 XD61...

Page 13: ...XD14 P4C0 P8B0 ULPI_DATA 0 7 XD15 P4C1 P8B1 XD16 P4D0 P8B2 XD17 P4D1 P8B3 XD18 P4D2 P8B4 XD19 P4D3 P8B5 XD20 P4C2 P8B6 XD21 P4C3 P8B7 XD22 P1G0 ULPI_DIR XD23 P1H0 ULPI_CLK XD24 P1I0 CODEC_ADC_DATA XD2...

Page 14: ...TP3 TP4 CLOCK_GEN CLK_13M MCLK_SEL MCLK MCLK_BUF1 MCLK_BUF2 CODEC SDOUT MDIV2 RST_N SDIN SCLK LRCK MCLK NC7SZ175 U1 2 4 5 6 1 3 D CP C_N VCC Q GND D Q C 3V3 3V3 3V3 C1 100N TP5 TP6 LEDB GREEN 3V3 R1 1...

Page 15: ...0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 X0D55 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 X0D35 IO HEADER_RA J4 20 18 19 17...

Page 16: ...138 2 1 3 D G S R24 10K C34 33P 2M2 R20 X2 24M576 HC49US 33P C35 BSS138 Q3 2 1 3 D G S 10K R25 11M2896 HC49US X3 1K R22 3V3 MCLK_SEL NC7SZ157 U11 2 4 5 6 1 3 I0 I1 S VCC Q GND 0 1 U9 NC7SZU04 3 5 2 4...

Page 17: ...19 18 21 24 8 5 22 23 17 20 6 12 3 1 13 4 2 LRCK SCLK MDIV2 SDIN MCLK MDIV1 DGND AGND VQ AOUTB AOUTA VD VLC MUTEB_N MUTEA_N FILTP VA AINA AINB RST_N I2S LJ_N M0 M1 SDOUT MCLK 100P C47 6K8 R31 2K7 R38...

Page 18: ...se the XMOS Tools to program XMOS event driven processor devices The most up to date information on the board including schematics and product datasheets is available from http www xmos com usbaudio2...

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