XMOS XS1-L1, Manual

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USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0) 15/18
A
XC-6 USB AUDIO
SEPT 14 2009
1
1
L1_128_USB
SHEET NAME
PROJECT NAME
REV
DATE SIZE
OF
SHEET
A2
Copyright (c) 2009 XMOS Ltd.
XS1_L1_128TQFP U3
18 56 58 63 62 61 21 55 53 52 51 42 25
CLK DEBUG MODE0 MODE1 MODE2 MODE3 RST_N TCK TDI TDO TMS TRST_N RESERVED
CONFIG
+1V0
C7 1N
NCP303LSN09 U8
4
2 3
1
5
CD
RST_OUT
GND INPUT
NC
47K
R8
X0D50 X0D51 X0D52 X0D53
GREEN
D3
X0D54 X0D55
1K
R11
100N C9 C10 100N
C11 100N
100N C12
C13 100N
C14 100N
100N C15
C16 100N
C17 100N
100N C18
100N C19
+3V3 +1V0
C20 100N
XS1_L1_128TQFP U3
24
46 45
22 19 20 23
108 101 123 120
93 79 73 64
103 111
116 99 92 91 88 80 78 71 66 65 60 57 54 43 41 40 39 17 129
32 26 15
1
44 50 77 74 68 59 49 29 12 83
48 47
PLL_AGND PLL_AVDD
VDD_83 VDD_12 VDD_29 VDD_49 VDD_59 VDD_68 VDD_74 VDD_77 VDDIO_50 VDDIO_44 VDDIO_1 VDDIO_15 VDDIO_26 VDDIO_32
GND_PAD
GND_17 GND_39 GND_40 GND_41 GND_43 GND_54 GND_57 GND_60 GND_65 GND_66 GND_71 GND_78 GND_80 GND_88 GND_91 GND_92 GND_99
GND_116
VDDIO_111 VDDIO_103 VDDIO_64 VDDIO_73 VDDIO_79 VDDIO_93 VDDIO_120 VDD_123 VDD_101 VDD_108 PCU_GATE PCU_WAKE PCU_VDD PCU_VDDIO
OTP_VDDIO
OTP_VPP
PCU_CLK
POWER
4R7
R18
+1V0
1U C3
+3V3
+1V0 +3V3
+1V0
+3V3
XS1_L1_128TQFP
U3
67 112 114 117 119 121 122 124 125 127 3 38 35 33 31 13 11 9 8 6 4 95 97 98 100 75 76 81 82 69 70 72 102 104 105 109 84 85 86 87 89 94 90 96 106 107 110 113 115 118 126 128 2 5 7 10 14 16 27 28 30 34 36 37
X0D0 X0D1 X0D2 X0D3 X0D4 X0D5 X0D6 X0D7 X0D8 X0D9
X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 X0D55 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 X0D35
IO
HEADER_RA
J4
20 18
19 17
1
16 14 12
11 13 15
3 5 7 9
2 4 6 8 10
+3V3
+5V
CLK
X0D0 X0D10 X0D11 X0D24 X0D34
1MBIT AT25FS010 U4
1 6
2
5
4 8
3 7
HOLD_N WP_N
VCC GND
SI
SO
SCK CS_N
+3V3
+3V3
R12
10K
+3V3
+3V3
100N C21
+5V
R9
47K
+3V3
X0D66 X0D65 X0D64 X0D63 X0D62 X0D61 X0D58 X0D57 X0D56
4U7
C4
+5V
2U2 C26
+3V3
NCP699SN33 U6
4
5
1 3
2
GND
EN VIN
VOUT
NC
10K
R13
U7 NCP1521B
4
5
1 3
2
GND
EN VIN
LX FB
6K8
R7
330P C6
L1
2U2
C8 10U
+1V0
100N
C22
X0D25 X0D35 X0D36
100N C23
+3V3
U2 USB3318
19 8 9 10 11 13 14 15
17 21
12
1 7
22 23
16 20 18
4 2 3 5 6
25 24
RBIAS
GND
DP DM VBAT VBUS VDD33
NXT STP
DATA0
REFCLK RESETB CPEN ID
CLKOUT
VDD18 VDDIO
DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
DIR
DNP
R17
10N C5
8K06
R6
+1V8
+3V3
C24 100N
USB_B J3
6 4 5 2 1 3
DP
VBUS
DM S1
GND
S2
100N
C25
NCP699SN18 U5
4
5
1 3
2
GND
EN VIN
VOUT
NC
2U2 C27
10K
R14
+1V8
+5V
1700mA
330R
FB1
+5V
1K
R10
TRST_N
TRST_N
TD2
TD2
TD1
TD1
TMS
TMS
TCK
TCK
NC
PHY_RST_N
PHY_RST_N
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC
NC
NC NC
ULPI_DATA0
ULPI_DATA0
ULPI_DIR
ULPI_DIR
NC
NC
ULPI_DATA7
ULPI_DATA7
ULPI_DATA6
ULPI_DATA6
ULPI_DATA5
ULPI_DATA5
ULPI_DATA4
ULPI_DATA4
ULPI_DATA3
ULPI_DATA3
ULPI_DATA2
ULPI_DATA2
ULPI_DATA1
ULPI_DATA1
NC
X0D1
X0D1
NC
NC NC
USB_DM USB_DP
ULPI_NXT
ULPI_NXT
ULPI_STP
ULPI_STP
ULPI_CLK
ULPI_CLK
X0D0
X0D0
X0D10
X0D10
X0D11
X0D11
NC NC
CLK
CLK
CLK
SRST_N
SRST_N
SRST_N
DEBUG
DEBUG
NC NC NC NC
NC NC NC NC
NC NC NC NC
XSYS2
SPI FLASH
USB_VBUS
USB PHY
ALL MODE PINS HAVE INTERNAL PULLUPS MODE[3:2] = 11 ==> BOOT FROM SPI MODE[1:0] = 00 ==> PLL_MULT = 30.75 ==> 13MHZ REFCLK MODE[3:2] = 00 ==> BOOT FROM JTAG (DON'T BOOT)
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