Xilinx Virtex-II Pro, User Manual

Page: 22 / 30

22 www.xilinx.com Virtex-II Pro Prototype Platform User Guide
1-800-255-7778 UG027 / PN 0402044 (v1.6) October 25, 2002
Chapter 1: Virtex-II Pro Prototype Platform
R
19. SDRAM Pins
The system clock that enables proper communication between the SDRAM and the DUT is
GCLK1P.
Table 1-10 shows the system clock pin locations for the available DUT package
types.
Table 1-11 shows the pin mapping from the SDRAM to the available DUT package types.
Table 1-10: System Clock for SDRAM and DUT
SDRAM Pin FG456 FF672 FF1152
CLK E12 D14 D18
Table 1-11: SDRAM to FPGA Pin Mapping
SDRAM Pin FG456 FF672 FF1152
DQ0 T2 H3 N8
DQ1 T3 J4 N9
DQ2 T1 H4 N10
DQ3 R1 G4 M6
DQ4 R2 G3 N4
DQ5 N2 E3 M4
DQ6 U2 J3 N7
DQ7 N1 E4 M7
DQ8 Y1 N4 AB2
DQ9 M3 K4 W10
DQ10 W2 N3 AA3
DQ11 V1 M3 Y6
DQ12 V2 M4 AA2
DQ13 N4 L3 Y7
DQ14 M4 K3 W9
DQ15 N3 L1 W8
DQ16 K4 N2 L4
DQ17 H1 G1 M3
DQ18 K3 L2 L5
DQ19 K1 J1 P7
DQ20 K2 K1 L6
DQ21 J2 J2 P8
DQ22 H3 H2 M2
DQ23 J1 H1 N1
DQ24 F2 E2 K1
DQ25 G1 E1 L3
DQ26 F1 D1 K2