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Virtex-II Pro Prototype Platform User Guide
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UG027 / PN 0402044 (v1.6) October 25, 2002
Appendix A: RISCWatch and RISCTrace Interfaces
R
Table A-1:
JTAG Connector Signals for RISCWatch
Pin
RISCWatch
Description
I/O
Signal Name
1
Input
TDO
JTAG test-data out.
2
No Connect
Reserved
3
Output
TDI
1
JTAG test-data in.
4
Output
TRST
JTAG test reset.
5
No Connect
Reserved
6
Output
+Power
2
Processor power OK
7
Output
TCK
3
JTAG test clock.
8
No Connect
Reserved
9
Output
TMS
JTAG test-mode select.
10
No Connect
Reserved
11
Output
HALT
Processor debug halt mode.
12
No Connect
Reserved
13
No Connect
Reserved
14
KEY
No pin should be placed at this position.
15
No Connect
Reserved
16
GND
Ground
Notes:
1. A 10K
Ω
pull-up resistor should be connected to this signal to reduce chip-power consumption. The
pull-up resistor is not required.
2. The +POWER signal, is provided by the board, and indicates whether the processor is operating. This
signal does not supply
power
to the debug tools or to the processor. A series resistor (1K
Ω
or less)
should be used to provide short-circuit current-limiting protection.
3. A 10K
Ω
pull-up resistor must be connected to these signals to ensure proper chip operation when
these inputs are not used.
Table A-2:
PPC405x3 to RISCWatch Signal Mapping
PPC405x3
RISCWatch
JTAG
Connector
Pin
Mictor
Connector
Pin
Signal
I/O
Signal
I/O
C405JTGTDO
1
Output
TDO
Input
1
11
JTGC405TDI
Input
TDI
Output
3
19
JTGC405TRSTNEG
Input
TRST
Output
4
21
JTGC405TCK
Input
TCK
Output
7
15
JTGC405TMS
Input
TMS
Output
9
17
DBGC405DEBUGHALT
2
Input
HALT
Output
11
7
Notes:
1. This signal must be driven by a tri-state device using
C405JTGTDOEN as the enable signal.
2. This signal must be inverted between the PPC405x3 and the RISCWatch.
