Spartan-3A/3AN FPGA Starter Kit Board User Guide
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81
UG334 (v1.1) June 19, 2008
SPI Communication
R
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first DAC_OUT value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.
Communication Protocol
Figure 10-4
shows the communications protocol required to interface with the LTC2624
DAC. The DAC supports both 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the DAC, the SPI interface is formed by a 32-bit shift register. Each 32-bit command
word consists of a command and an address, followed by a data value. As a new command
enters the DAC, the previous 32-bit command word is echoed back to the master. The
response from the DAC can be ignored although it is a useful to confirm correct
communication.
Figure 10-3:
SPI Communication Waveforms
DAC_CS
SPI_MOSI
SPI_SCK
DAC_OUT
Previous 31
31
30
29
Previous 30
Previous 29
UG330_c9_03
_071906
Figure 10-4:
SPI Communications Protocol to LTC2624 DAC
31
0
x x
x x
x x
x x
x x
x x
9 10
a
0
a
1
a
2
a
3
c
0
c
1
c
2
c
3
11
8
7
6
5
4
3
2
1
0
ADDRESS
a
3
a
2
a
1
a
0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
All
DAC A
DAC B
DAC C
DAC D
1 1 1 1
SPI_MOSI
SPI_SCK
DAC_CS
DAC_OUT
12-bit Unsigned
COMMAND
Don’t Care
UG334_c10_04_052407
msb
lsb
Don’t Care
DATA
Slave:
LTC2624 DAC
Master
FPGA
