Xilinx Spartan-3A DSP FPGA Series, User Manual, Page: 110 / 140

110 www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
Chapter 13: DDR2 SDRAM
R
UCF Location Constraints
Address
Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR2 SDRAM
address pins, including the I/O pin assignment and the I/O standard used.
Mis
ce
lla
neo
u
s
SD_LOOP_IN H4 I/O self-calibration loop. Direction can be
reversed if more convenient in the FPGA
application.
SD_LOOP_OUT H3
SD_ODT P1 DDR2 SDRAM on-device termination control
Table 13-1: FPGA-to-DDR2 SDRAM Connections (Continued)
Category
DDR2 SDRAM
Signal Name
FPGA Pin
Number Function
Figure 13-2: UCF Location Constraints for DDR2 SDRAM Address Inputs
NET "SD_A<15>" LOC = "W3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<14>" LOC = "V4" | IOSTANDARD = SSTL18_II ;
NET "SD_A<13>" LOC = "V3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<12>" LOC = "Y2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<11>" LOC = "V1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<10>" LOC = "T3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<9>" LOC = "W2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<8>" LOC = "W1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<7>" LOC = "Y1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<6>" LOC = "U1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<5>" LOC = "U4" | IOSTANDARD = SSTL18_II ;
NET "SD_A<4>" LOC = "U2" | IOSTANDARD = SSTL18_II ;
NET "SD_A<3>" LOC = "U3" | IOSTANDARD = SSTL18_II ;
NET "SD_A<2>" LOC = "R1" | IOSTANDARD = SSTL18_II ;
NET "SD_A<1>" LOC = "T4" | IOSTANDARD = SSTL18_II ;
NET "SD_A<0>" LOC = "R2" | IOSTANDARD = SSTL18_II ;