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Xilinx Spartan-3A DSP FPGA Series User Manual Download Page 49

Spartan-3A/3AN FPGA Starter Kit Board User Guide

www.xilinx.com

49

UG334 (v1.1) June 19, 2008

LCD Controller

R

Disabled

If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.

Clear Display

Clears the display and returns the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM 

addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option 

settings. The I/D control bit is set to 1 (increment address counter mode) in the 

Entry Mode 

Set

 command.

Execution Time: 82

µ

s – 1.64 ms 

Return Cursor Home

Returns the cursor to the home position, the top-left corner. DD RAM contents are 

unaffected. Also returns the display being shifted to the original position, shown in 

Figure 5-3

. 

The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its 

original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40

µ

s – 1.6 ms

Entry Mode Set

Sets the cursor move direction and specifies whether or not to shift the display. 
These operations are performed during data reads and writes.
Execution Time: 40

µ

s 

Bit DB1: (I/D) Increment/Decrement

This bit either auto-increments or auto-decrements the DD RAM and CG RAM address 

counter by one location after each 

Write Data to CG RAM or DD RAM

 command or 

Read 

Function Set

0

0

0

0

1

0

1

0

-

-

Set CG RAM Address

0

0

0

1

A5

A4

A3

A2

A1

A0

Set DD RAM Address

0

0

1

A6

A5

A4

A3

A2

A1

A0

Read Busy Flag and Address

0

1

BF

A6

A5

A4

A3

A2

A1

A0

Write Data to CG RAM or DD RAM

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Read Data from CG RAM or DD RAM

1

1

D7

D6

D5

D4

D3

D2

D1

D0

Table 5-2:

LCD Character Display Command Set (4-bit mode) 

(Continued)

Function

LC

D

_

R

S

LCD_R

W

Upper Nibble

Lower Nibble

DB

7

DB

6

DB

5

DB

4

DB

3

DB

2

DB

1

DB

0

0

Auto-decrement address counter. Cursor/blink moves to left.

1

Auto-increment address counter. Cursor/blink moves to right.

Summary of Contents for Spartan-3A DSP FPGA Series

Page 1: ...R Spartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008...

Page 2: ...ESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEM...

Page 3: ...omponents and Features 19 Design Trade Offs 21 Configuration Methods Galore 21 Voltages for all Applications 21 Spartan 3A 3AN FPGA Starter Kit Design Examples 21 Choose a Spartan 3 Generation Starter...

Page 4: ...ector 34 UCF Constraints 34 Location 34 Clock Period Constraints 35 Related Resources 35 Chapter 4 FPGA Configuration Options Configuration Mode Jumpers 39 Xilinx Platform Flash Configuration PROM s 4...

Page 5: ...Resources 55 Chapter 6 VGA Display Port Signal Timing for a 60 Hz 640x480 VGA Display 58 VGA Signal Timing 60 UCF Location Constraints 61 Related Resources 61 Chapter 7 RS 232 Serial Ports Overview 6...

Page 6: ...sources 89 Chapter 12 SPI Serial Flash SPI Flash PROM Select Jumpers J1 93 Shared SPI Flash and Platform Flash Data Line 94 Jumper Settings to Configure FPGA from Selected SPI Flash PROM 94 UCF Locati...

Page 7: ...erential I O Connectors 124 Using Differential Inputs 125 Using Differential Outputs 126 Differential Trace Layout Considerations 126 34 Conductor Cable Assemblies 2x17 128 UCF Location Constraints 12...

Page 8: ...8 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 R...

Page 9: ...ard The following table describes the different kits Almost all functionality is identical between the Revision C and Revision D boards although the silkscreen changes make the two boards look differe...

Page 10: ...following chapters Chapter 1 Introduction and Overview provides an overview of the key features of the Spartan 3A 3AN Starter Kit board Chapter 2 Switches Buttons and Rotary Knob defines the switches...

Page 11: ...y interface Chapter 14 10 100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface Chapter 15 Expansion Connectors describes the various...

Page 12: ...12 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Preface About This Guide R...

Page 13: ...tion of the board jumpers as shown in Figure 1 2 page 14 These settings are required for the demonstration design to configure correctly 2 Optionally connect a VGA display device The display device ca...

Page 14: ...nnect a PC directly to the board using a standard 9 pin serial cable For more information on the demonstration design visit the Design Examples web page Spartan 3A 3AN FPGA Starter Kit Demo Design Ove...

Page 15: ...b Figure 2 5 page 27 is pressed the display automatically rotates a graphic image and zooms in and out around the image This is called AutoPilot mode A brief text overview describing the board appears...

Page 16: ...ry knob This action causes the FPGA to load the selected image from external Flash memory To change to the Scroll or Rotate Graphic mode press the rotary knob Table 1 1 Function of Each Menu Control P...

Page 17: ...erence_designs htm demo 1 Device DNA Reader Reads the FPGA s unique Device ID value and displays it on the character LCD screen www xilinx com products boards s3astarter reference_designs htm dna_read...

Page 18: ...treams have the power saving Suspend mode enabled Suspend mode reduces FPGA power consumption while preserving the present state of the FPGA application and the FPGA s configuration data Set the SUSPE...

Page 19: ...port to the board s DCE connector see Figure 7 1 page 63 When the demonstration design begins operating it transmits a message using the serial port Press a number key on the PC to load the associate...

Page 20: ...g solution FPGA download debug SPI serial Flash in system direct programming 50 MHz clock oscillator 8 pin DIP socket for second oscillator SMA connector for clock inputs or outputs 100 pin Hirose FX2...

Page 21: ...lly to power Spartan 3 generation FPGAs This regulator is sufficient for most standalone FPGA applications Spartan 3A 3AN FPGA Starter Kit Design Examples Visit the Spartan 3A 3AN FPGA Starter Kit Des...

Page 22: ...memory to verify contents Download complete configuration images using standard MCS files Manually program individual bytes Display the device identifier and 64 bit unique device numbers Spartan 3A 3...

Page 23: ...rtan 3 PCI Express Starter Kit Spartan 3 PCI Express Starter Kit HW S3PCIE DK www xilinx com s3pcie For simple Spartan 3 FPGA applications consider the fairly basic Spartan 3 Starter Kit board Spartan...

Page 24: ...al information Spartan 3A 3AN Starter Kit www xilinx com s3astarter Spartan 3A 3AN Rev D Starter Kit user guide this document Spartan 3A Rev C Starter Kit user guide www xilinx com support documentati...

Page 25: ...nnects the FPGA pin to 3 3V a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce There is...

Page 26: ...WAKE LED page 32 To enable Suspend mode add the configuration string shown in Figure 2 4 to the user constraints file UCF If Suspend mode is not enabled in the application then the SUSPEND switch has...

Page 27: ...as shown in Figure 2 6 Use an internal pull down resistor within the FPGA pin to generate a logic Low when the button is not pressed Figure 2 7 shows how to specify a pull down resistor within the UC...

Page 28: ...ree outputs The two shaft encoder outputs are ROT_A and ROT_B The center push button switch is ROT_CENTER Operation The rotary push button switch integrates two different functions The switch shaft ro...

Page 29: ...a pull up resistor within the FPGA pin pulls the signal to a logic High The UCF constraints in Figure 2 11 describe how to define the pull up resistor The FPGA circuitry to decode the A and B inputs...

Page 30: ...Ds are labeled LED7 through LED0 LED7 is the left most LED LED0 the right most LED Figure 2 10 Outputs from Rotary Shaft Encoder Might Include Mechanical Chatter A B Detent Detent UG230_c2_07_030606 R...

Page 31: ...onal Discrete LEDs The Spartan 3A 3AN Starter Kit board provides two optional LEDs shown in Figure 2 14 Depending on which features are used by an application these LED connections may be also used as...

Page 32: ...e the INIT_B pin is reserved and signals a CRC error after configuration If such an error occurs the FPGA drives INIT_B Low lighting the LED If using the INIT_B pin as a user I O pin after configurati...

Page 33: ...on board 50 MHz clock oscillator Clocks can be supplied off board via an SMA style connector Alternatively the FPGA can generate clock signals or other high speed signals on the SMA style connector A...

Page 34: ...Manager DCM to generate or synthesize other frequencies from the on board 50 MHz or 133 MHz oscillator Caution Be aware of the pin 1 orientation on the crystal oscillator when installing it in the as...

Page 35: ...hich equates to a 20 ns period The output duty cycle from the oscillator ranges between 40 to 60 Related Resources Refer to the following links for additional information Epson SG 8002JF Series Oscill...

Page 36: ...36 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 3 Clock Sources R...

Page 37: ...erial mode Program the on board 16 Mbit STMicroelectronics SPI serial Flash PROM or the 16 Mbit Atmel SPI based DataFlash PROM then configure the FPGA from the image stored in the SPI serial Flash PRO...

Page 38: ...lly finishes configuration Pressing the PROG button forces the FPGA to restart its configuration process The Xilinx Platform Flash PROM provides easy JTAG programmable configuration storage for the FP...

Page 39: ...AN Starter Kit Board only This mode configures a Spartan 3AN FPGA using the internal In System Flash memory This mode is not supported on the Spartan 3A Starter Kit board Master Serial 0 0 0 Platform...

Page 40: ...mode the Platform Flash PROM must be disabled PROG Push Button Switch The PROG push button switch labeled in Figure 4 1 forces the FPGA to reconfigure from the configuration memory source selected by...

Page 41: ...e USB Cable The kit includes a standard USB Type A Type B cable similar to the one shown in Figure 4 2 The actual cable color might vary from the picture The wider and narrower Type A connector fits t...

Page 42: ...f the Xilinx software is programming firmware updates to the USB interface Platform Flash Programming Example in Spartan 3 Generation Configuration User Guide The Spartan 3 Generation Configuration Us...

Page 43: ...igh Once mastered the LCD is a practical way to display a variety of information using standard ASCII and custom characters However these displays are not fast Scrolling the display at half second int...

Page 44: ...drives the data lines when LCD_RW is High Most applications treat the LCD as a write only peripheral and never read from the display UCF Location Constraints Figure 5 2 provides the UCF constraints fo...

Page 45: ...re 80 total character locations in DD RAM with 40 characters available per line Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non display data Alternatively these locati...

Page 46: ...ion as defined by the I D set by the Entry Mode Set command CG ROM The Character Generator ROM CG ROM contains the font bitmap for each of the predefined characters that the LCD screen can display sho...

Page 47: ...0x07 in a DD RAM location CG RAM The Character Generator RAM CG RAM provides space to create eight custom character bitmaps Each custom character location consists of a 5 dot by 8 line bitmap as show...

Page 48: ...re used the upper three data bits are don t care positions The eighth row of bitmap data is usually left as all zeros to accommodate the cursor Command Set Table 5 2 summarizes the available LCD contr...

Page 49: ...to its original status if it was shifted The cursor or blink move to the top left character location Execution Time 40 s 1 6 ms Entry Mode Set Sets the cursor move direction and specifies whether or n...

Page 50: ...This function positions the cursor in order to modify an individual character or to scroll the display window left or right to reveal additional data stored in the DD RAM beyond the 16th character on...

Page 51: ...is in progress The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute This command also returns the present value of the addr...

Page 52: ...ation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command However a display shift is not executed during read operations Execution Time 40 s Operation...

Page 53: ...sequential four bit operations Each eight bit transfer must be decomposed into two four bit transfers spaced apart by at least 1 s as shown in Figure 5 6 The upper nibble is transferred first followed...

Page 54: ...n the Spartan 3A 3AN Starter Kit board 2 Issue an Entry Mode Set command 0x06 to set the display to automatically increment the address pointer 3 Issue a Display On Off command 0x0C to turn the displa...

Page 55: ...lowing links for additional information PowerTip PC1602 D Character LCD Basic Electrical and Mechanical Data www powertipusa com pdf pc1602d pdf Sitronix ST7066U Character LCD Controller www samsung c...

Page 56: ...56 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 5 Character LCD Screen R...

Page 57: ...p of the board The FPGA directly drives the five VGA signals via resistors Each red green and blue signal has four outputs from the FPGA that feed a resistor divider tree This approach Figure 6 1 VGA...

Page 58: ...fied published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive the VGA mo...

Page 59: ...cal display pass The display resolution defines the size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated Modern VGA dis...

Page 60: ...nction of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defin...

Page 61: ...w rate and the output drive current Related Resources Refer to the following links for additional information VESA www vesa org VGA timing information www epanorama net documents pc vga_timing html Fi...

Page 62: ...62 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 6 VGA Display Port R...

Page 63: ...h serial cable For typical applications the board does not require null modem cables gender changers or crossover cables Use the DTE style connector to control other RS 232 peripherals such as modems...

Page 64: ...dem cable In this example both the FPGA and the external serial device are driving data on the transmit line Hardware flow control is not supported on the connector The port s DCD DTR and DSR signals...

Page 65: ...oard directly to the board Also see Adding a Second PS 2 Port Using a Y Splitter Cable page 69 Figure 8 1 PS 2 Connector Location and Signals Table 8 1 PS 2 Connector Pinout PS 2 DIN Pin Signal FPGA P...

Page 66: ...a signals are only driven when data transfers occur otherwise they are held in the idle state at a logic High The timing defines signal requirements for mouse to host communications and bidirectional...

Page 67: ...psLock 58 Shift 12 Ctrl 14 1 16 2 1E 3 26 4 25 5 2E Q 15 W 1D E 24 R 2D T 2C A 1C S 1B D 23 F 2B G 34 Z 1Z X 22 C 21 V 2A B 32 6 36 7 3D 8 3E 9 46 0 45 _ 4E 55 Back Space 66 Y 35 U 3C I 43 O 44 P 4D 5...

Page 68: ...he 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 an...

Page 69: ...ll connect a mouse or a keyboard directly to the Spartan 3A 3AN Starter Kit board connector These applications use the primary FPGA connections to the PS 2 port as shown in Figure 8 1 page 65 However...

Page 70: ...on PS 2 Mouse Keyboard Protocol www computer engineering org ps2protocol PS 2 Keyboard Interface www computer engineering org ps2keyboard PS 2 Mouse Interface www computer engineering org ps2mouse Fig...

Page 71: ...ists of a Linear Technology LTC6912 1 programmable pre amplifier that scales the incoming analog signal on the J22 header The output of the pre amplifier connects to a Linear Technology LTC1407A 1 ADC...

Page 72: ...btracted from the input voltage on VINA or VINB The maximum range of the ADC is 1 25V centered around the reference voltage 1 65V Hence 1 25V appears in the denominator to scale the analog input accor...

Page 73: ...are shared with other devices on the SPI bus The AMP_CS signal is the active Low slave select input to the amplifier Programmable Gain Each analog channel has an associated programmable gain amplifie...

Page 74: ...SPI_SCK clock signal The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK The amplifier interface is relatively slow supporting only about a 10 MHz clock frequency 5 0 0 1 1...

Page 75: ...DC When the AD_CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD_CONV is asserted a latency of one sampl...

Page 76: ...1 D2 D3 D0 D5 D6 D7 D4 D9 D10 D11 D8 D13 D12 Z Z Z 13 13 0 0 ADC_OUT SPI_SCK AD_CONV 13 Channel 0 Channel 0 Channel 1 Sample point Sample point Converted data is presented with a latency of one sample...

Page 77: ...efer to the following links for additional information Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http www li...

Page 78: ...78 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 9 Analog Capture Circuit R...

Page 79: ...45 connector as shown in Figure 10 1 SPI Communication As shown in Figure 10 2 the FPGA uses a Serial Peripheral Interface SPI to communicate digital values to each of the four DAC channels The SPI b...

Page 80: ...e SPI_SCK clock signal The bus is fully static and supports clock rates up to the maximum of 50 MHz However check all timing parameters using the LTC2624 data sheet if operating at or close to the max...

Page 81: ...e DAC Communication Protocol Figure 10 4 shows the communications protocol required to interface with the LTC2624 DAC The DAC supports both 24 bit and 32 bit protocol The 32 bit protocol is shown Insi...

Page 82: ...ference voltage Channels C and D have a separate reference voltage nominally also 3 3V supplied by the LP3906 regulator designated as IC18 The reference voltage for Channels C and D can be modified as...

Page 83: ...e various images using the FPGA s MultiBoot feature Stores and executes MicroBlaze processor code directly from the Flash memory Stores MicroBlaze processor code in the Flash memory and shadows the co...

Page 84: ...e not used In general the Flash memory device connects to the FPGA to support Byte Peripheral Interface BPI configuration as described in Table 11 1 Table 11 1 FPGA to Flash Connections Category NOR F...

Page 85: ...n asserts NF_BYTE High use NF_A0 to carry the D15 signal Connect the other higher order data lines to FPGA user I Os NF_D14 R21 NF_D13 T22 NF_D12 U22 NF_D11 U21 NF_D10 V22 NF_D9 W22 NF_D8 T20 NF_D7 Y9...

Page 86: ...le Connects to FPGA pin LDC0 to support the BPI configuration 0 Enabled 1 Disabled NF_OE W19 Active Low Flash Chip Enable Connects to FPGA pin LDC1 to support the BPI configuration 0 Enable data outpu...

Page 87: ...33 DRIVE 8 SLEW SLOW NET NF_A 18 LOC F22 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET NF_A 17 LOC H20 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET NF_A 16 LOC H21 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET N...

Page 88: ...MOS33 DRIVE 8 SLEW SLOW NET NF_D 9 LOC W22 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET NF_D 8 LOC T20 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET NF_D 7 LOC Y9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET NF...

Page 89: ...information on how to create and format FPGA configuration images for parallel Flash To program the parallel Flash memory see the associated design example UG332 Spartan 3 Generation Configuration Use...

Page 90: ...90 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 11 Parallel NOR Flash PROM R...

Page 91: ...erial DataFlash PROM The SPI serial Flash is useful in a variety of applications The SPI Flash provides a possible means to configure the FPGA a new feature in Spartan 3E and Spartan 3A 3AN FPGAs The...

Page 92: ...ion User I O pin after configuration SPI_SS_B Y4 FPGA PROM Asynchronous active Low slave select signal Actively drives Low during SPI Flash configuration mode User I O pin after configuration Drive Hi...

Page 93: ...ly then the FPGA configures from the Atmel SPI Flash PROM After configuration the FPGA application selects the Atmel PROM using the SPI_SS_B signal and the STMicro PROM using the ALT_SS_B signal If bo...

Page 94: ...n Table 12 4 Disable the Platform Flash PROM using Jumper J46 shown in Table 12 4 Select one of the SPI serial Flash PROMs as the SPI configuration source as shown in Table 12 2 Table 12 3 Possible Po...

Page 95: ...g programming Hold the FPGA s PROG_B input Low using jumper J16 to place the I Os in Hi Z the FPGA s DONE pin remains Low Using the Indirect Programming Method the programming cable connects to the FP...

Page 96: ...rallel Programming Cable Optional page 97 3 Locate the J1 J23 and J25 jumpers in the upper right corner of the board using Figure 12 1 as a guide Figure 12 4 also provides a reference diagram Table 12...

Page 97: ...G_B pin must be held Low Insert a jumper in jumper J16 as shown in Figure 12 4 This holds all the FPGA s I O in three state to allow the JTAG programmer full access to the SPI PROM pins 9 Re apply pow...

Page 98: ...The labels on the JTAG3 cable face toward the J11 jumpers If using flying leads they must be connected as shown in Figure 12 5b and Table 12 6 Note the color coding for the leads The gray INIT lead is...

Page 99: ...PI Serial Flash R 4 Select a previously formatted PROM file as shown in Figure 12 7 5 Click Open 6 Select the Part Name for a supported SPI serial Flash as shown in Figure 12 8 7 Click OK Figure 12 7...

Page 100: ...Program Note Step 14 occurs later 10 Click the Programming Properties option under Category as shown in Figure 12 10 11 Check Verify Unchecking Verify reduces programming time but the iMPACT software...

Page 101: ...GA s DONE pin is High and the DONE LED remains lit throughout the programming process Note Any information displayed on the LCD screen remains on the screen throughout the programming process If it ap...

Page 102: ...amming Using iMPACT To program the attached and selected SPI PROM using the iMPACT software and the Indirect programming method follow the steps outlined below 1 Invoke iMPACT and select Configure dev...

Page 103: ...in iMPACT 9 2i This file is not the special FPGA based SPI programming application 4 Select Enable Programming of SPI Flash Device Attached to this FPGA 5 Click Open 6 The iMPACT software warns that...

Page 104: ...shown in Figure 12 14 select the programming file for the attached SPI Flash PROM 8 Click Open 9 Select the part number for the attached SPI Flash PROM as shown in Figure 12 15 10 Click OK Figure 12 1...

Page 105: ...e 12 17 the iMPACT software then displays the JTAG chain for the XC3S700A Spartan 3A FPGA followed by the XCF04S Platform Flash PROM A similar display will be seen for the XC3S700AN Spartan 3AN FPGA C...

Page 106: ...e FPGA is configured with the new programming file Related Resources Refer to the following links for additional information Xilinx Parallel Cable IV with Flying Leads www xilinx com onlinestore progr...

Page 107: ...5 0 M3 FPGA SD_DQ 15 0 SD_BA 2 0 SD_RAS A 12 0 BA 1 0 DQ 15 0 RAS Micron 512Mb DDR2 SDRAM SD_CAS SD_WE SD_CK_P SD_CK_N SD_CKE SD_CS SD_LDM SD_UDM SD_UDQS_P SD_LDQS_N CAS WE UDM UDQS LDM LDQS CS CK CK...

Page 108: ...Kit Schematic All DDR2 SDRAM interface signals are terminated See DDR2 SDRAM Termination Network in the Starter Kit Schematic for information on the SSTL18 termination scheme used on the board DDR2 S...

Page 109: ...L5 SD_DQ3 L3 SD_DQ2 K1 SD_DQ1 K5 SD_DQ0 H1 Control SD_BA2 P5 Bank address inputs SD_BA1 R3 SD_BA0 P3 SD_RAS M3 Command inputs SD_CAS M4 SD_WE N4 SD_CK_N M2 Differential clock input SD_CK_P M1 SD_CKE...

Page 110: ...ry DDR2 SDRAM Signal Name FPGA Pin Number Function Figure 13 2 UCF Location Constraints for DDR2 SDRAM Address Inputs NET SD_A 15 LOC W3 IOSTANDARD SSTL18_II NET SD_A 14 LOC V4 IOSTANDARD SSTL18_II NE...

Page 111: ...NDARD SSTL18_II NET SD_DQ 5 LOC L1 IOSTANDARD SSTL18_II NET SD_DQ 4 LOC L5 IOSTANDARD SSTL18_II NET SD_DQ 3 LOC L3 IOSTANDARD SSTL18_II NET SD_DQ 2 LOC K1 IOSTANDARD SSTL18_II NET SD_DQ 1 LOC K5 IOSTA...

Page 112: ...mory plus the strobe delay from the memory back to the FPGA Put another way the loopback trace must be one round trip time to and from the memory Also the loopback signal should be in the center of th...

Page 113: ...inx Embedded Development Kit EDK www xilinx com ise embedded_design_prod platform_studio htm MT47H32M16 32M x 16 DDR2 SDRAM Data Sheet download micron com pdf datasheets dram ddr2 512MbDDR2 pdf Multi...

Page 114: ...114 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 13 DDR2 SDRAM R...

Page 115: ...ysical layer PHY interface and an RJ 45 connector as shown in Figure 14 1 With an Ethernet Media Access Controller MAC implemented in the FPGA the board can optionally connect to a standard Ethernet n...

Page 116: ...PGA Pin Number Function E_TXD 4 B2 Transmit Data to the PHY E_TXD 4 is also the MII Transmit Error E_TXD 3 F7 E_TXD 2 E6 E_TXD 1 E7 E_TXD 0 F8 E_TX_EN D8 Transmit Enable E_TX_CLK E11 Transmit Clock 25...

Page 117: ...performance Refer to the OPB Ethernet MAC data sheet v1 02 for details The OPB clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6 5 MHz or faster for 10 Mbps Ethernet ope...

Page 118: ..._ethernetlite pdf EDK Documentation http www xilinx com ise embedded edk_docs htm Figure 14 3 UCF Location Constraints for 10 100 Ethernet PHY Inputs NET E_COL LOC G12 IOSTANDARD LVCMOS33 PULLDOWN NET...

Page 119: ...lus a differential clock or 12 single ended I O signals Two six pin Peripheral Module connections plus mounting holes for a third module Landing pads for an Agilent or Tektronix connectorless probe Fi...

Page 120: ...rd optionally provide limited differential I O capability on the FX2 connector The Spartan 3A 3AN Starter Kit board provides enhanced differential I O support using the Differential I O Connectors pag...

Page 121: ...pinout includes a few input only pins The Spartan 3A 3AN Starter Kit board pin assignment uses only full I O pins and are backwards compatible with the Spartan 3E Starter Kit board a Table 15 1 Hirose...

Page 122: ...ing board mounted and non locking cable connectors Hirose connectors http www hirose connectors com FX2 Series Connector Data Sheet http www hirose co jp cataloge_hp e57220088 pdf FX2_IO23 F18 28 28 G...

Page 123: ...ARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 15 LOC C19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 16 LOC D19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 17 LOC D18 IOSTANDARD LVCMOS33 SLEW FA...

Page 124: ...The J15 connector is primarily designed to transmit output data while the J2 connector is primarily designed to receive input data However both headers are equally good at transmitting differential d...

Page 125: ...le 15 4 Differential I O Connections and Header Connections Differential Pair Signal Name FPGA Ball FPGA Pin Name Signal Direction Header Pin Receive Header J2 Top Header RX_ 0 RXN_ 0 B4 IO_L31N_0 I O...

Page 126: ...ghts the differential I O signal traces These traces were routed for optimal signal integrity All differential pairs are routed with matched 100 impedance on the top board layer for maximum performanc...

Page 127: ...t Header J15 1 2 33 34 1 2 33 34 All traces routed with 100 matched impedance All receive pairs routed with matched trace lengths within 0 25 inches Receive clock pair connects to global clock inputs...

Page 128: ...8 inch C3AAG 3418M ND Flat ribbon cable multi color gold finish Figure 15 7 UCF Location Constraints for Receive and Transmit Headers High Speed LVDS Receive Connector RX NET RX_CLK_N LOC A11 IOSTANDA...

Page 129: ...e J18 header J18_IO 4 1 The board supplies 3 3V to the accessory board mounted in the J18 socket on the bottom pin J19 Header The J19 header shown in Figure 15 9 is left unpopulated on the board Four...

Page 130: ...abilities of programmable logic and embedded control boards They allow sensitive signal conditioning circuits and high power drive circuits to be placed where they are most effective near sensors and...

Page 131: ...ref cname PRODUCT ckey 351182 lc eng cc US Agilent 5404A 6A Pro Series Soft Touch Connector http www home agilent com agilent product jspx cc US lc eng pageMode OV pid 430362 ct PRODUCT id 430362 Tek...

Page 132: ...rless Debugging Port Landing Pads J34 Signal Name FPGA Pin Connectorless Landing Pads FPGA Pin Signal Name FX2_IO1 A13 A1 B1 GND GND FX2_IO2 B13 A2 B2 A14 FX2_IO3 GND GND A3 B3 B15 FX2_IO4 FX2_IO5 A15...

Page 133: ...ones to an attached set of headphones or to amplified speakers The audio device must use a 1 8th inch or 3 5 mm audio jack as shown in Figure 16 2 A stereo connector is highly recommended The FPGA sig...

Page 134: ...ew www xilinx com products boards s3astarter reference_designs htm demo Restoring the Out of the Box Flash Programming www xilinx com products boards s3astarter reference_designs htm out Figure 16 2 E...

Page 135: ...e 5 0V supply rail Caution Connect either the AC wall adapter OR use the through hole mounting pads but not both The 5 0V input voltage is then converted to the other supply voltages required by the b...

Page 136: ...rts the DDR2 SDRAM component itself and supplies the FPGA s I O Bank 3 which connects to the DDR2 SDRAM One high current 0 9V supplies the DDR2 SDRAM termination network A low current 1 8V supply is v...

Page 137: ...nabled Disconnect power to the board Remove the series jumper associated with the supply to be measured shown in Table 17 2 Locate jumper indicated in Figure 17 1 Connect a digital multimeter across t...

Page 138: ...ted in Table 17 3 the I2C interface can be controlled by the FPGA application using the I O pins indicated or by some external controller using the through hole mounting pads provided on the board sho...

Page 139: ...e 17 3 provides the UCF constraints for the I2C control signals to the regulators Related Resources Refer to the following link for additional information National Semiconductor LP3906 Dual High Curre...

Page 140: ...140 www xilinx comSpartan 3A 3AN FPGA Starter Kit Board User Guide UG334 v1 1 June 19 2008 Chapter 17 Voltage Supplies R...

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