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Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
Chapter 3:
Clock Sources
R
Clock Connections
Each of the clock inputs connect directly to a global buffer input. As shown in
Table 3-1
,
each of the clock inputs also optimally connects to an associated DCM.
Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time.
However, both inputs are available as clock inputs.
50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to ±2500 Hz or ±50 ppm.
Auxiliary Clock Oscillator Socket
A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The provided
eight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP) footprint.
Substitute the oscillator in this socket if the FPGA application requires a frequency other
than 50 MHz or 133 MHz. Alternatively, use the FPGA’s Digital Clock Manager (DCM) to
generate or synthesize other frequencies from the on-board 50 MHz or 133 MHz oscillator.
Caution!
Be aware of the pin 1 orientation on the crystal oscillator when installing it in the
associated socket.
SMA Clock Input or Output Connector
To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.
UCF Constraints
The clock input sources require two different types of constraints. The
location
constraints
define the I/O pin assignments and I/O standards. The
period
constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
Location
Figure 3-2
provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used.
Table 3-1:
Clock Inputs and Associated Global Buffers and DCMs
Clock Input
FPGA Pin
I/O Bank
Global Buffer
Associated DCM
LOC
CLK_50MHZ
E12
0
GCLK5
Top Right
DCM_X2Y3
CLK_AUX
V12
2
GCLK2
Bottom Right
DCM_X2Y0
CLK_SMA
U12
2
GCLK3