ML605 Hardware User Guide
www.xilinx.com
39
UG534
(v1.2.1) January 21, 2010
Detailed Description
12. USB-to-UART Bridge
The ML605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U34) which
allows connection to a host computer with a USB cable. The USB cable is supplied in this
evaluation kit (Type A end to host computer, Type Mini-B end to ML605 connector J21).
Table 1-14
details the ML605 J21 pinout.
Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx
XPS
UART Lite
. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit
(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the
CP2103GM USB-to-UART bridge to appear as a COM port to host computer
communications application software (for example, HyperTerm or TeraTerm). The VCP
device driver must be installed on the host PC prior to establishing communications with
the ML605. Refer to the evaluation kit
Getting Started Guide
for driver installation
instructions.
References
Refer to the
Silicon Labs
website for technical information on the CP2103GM and the VCP
drivers.
In addition, see some of the Xilinx UART IP specifications at:
•
http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf
•
http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf
Table 1-14:
USB Type B Pin Assignments and Signal Definitions
USB Connector
Pin
Signal Name
Description
1
VBUS
+5V from host system (not used)
2
USB_DATA_N
Bidirectional differential serial data (N-side)
3
USB_DATA_P
Bidirectional differential serial data (P-side)
4
GROUND
Signal ground
Table 1-15:
USB-to-UART Connections
U1 FPGA Pin
UART function
in FPGA
Schematic Net
Name
U34 CP2103GM
Pin
UART Function
in CP2103GM
T24
RTS, output
USB_1_CTS
22
CTS, input
T23
CTS, input
USB_1_RTS
23
RTS, output
J25
TX, data out
USB_1_RX
24
RXD, data in
J24
RX, data in
USB_1_TX
25
TXD, data out
