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www.xilinx.com
ML605 Hardware User Guide
UG534
(v1.2.1) January 21, 2010
Chapter 1:
ML605 Evaluation Board
Block Diagram
Figure 1-1
shows a high-level block diagram of the ML605 and its peripherals.
Related Xilinx Documents
Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources.
See
Appendix D, “References”
for a direct link to Xilinx documentation. See the following
locations for additional documentation on Xilinx tools and solutions:
•
ISE:
www.xilinx.com/ise
•
EDK:
www.xilinx.com/edk
•
Intellectual Property:
www.xilinx.com/ipcenter
•
Answer Browser:
www.xilinx.com/support
X-Ref Target - Figure 1-1
Figure 1-1:
ML605 High-Level Block Diagram
JTAG U
S
B Mini-B
U
S
B JTAG Circ
u
it
VITA 57.1 FMC
HPC Connector
VITA 57.1 FMC
LPC Connector
Virtex-6
FPGA
XC6VLX240T - 1FFG1156
S
y
s
tem ACE CF
S
.A. Comp
a
ctFl
as
h
S
.A. 8-
b
it MPU I/F
U
s
er LED/
S
W
U
s
er DIP
S
W
U
s
er LCD
200 MHz LVD
S
Clock
S
MA Clock
U
s
er
S
.E. 2.5V Clock
U
S
B Controller
Ho
s
t Type “A
”
Peripher
a
l Mini-B
Connector
s
CP210
3
U
S
B-TO-UART
Bridge
U
S
B Mini-B
Pl
a
tform Fl
as
h
Line
a
r BPI Fl
as
h
DVI Codec
VGA Video
DVI Video Connector
10/100/1000
Ethernet PHY
MII/GMII/RMII
S
Y
S
MON I/F
INIT, DONE LED
s
PROG PB, MODE
S
W
IIC B
us
IIC EEPROM
FMC HPC
DDR
3
S
ODIMM IIC
FMC LPC
S
FP Mod
u
le
Connector
S
GMII
PCIe X8 Edge Connector
MGT
S
MA REF Clock
MGT RX/TX
S
MA Port
UG5
3
4_01_092709
S
ODIMM
S
ocket
204-pin, DDR
3
Deco
u
pling C
a
p
s
MEM Vterm
Reg
u
l
a
tor
BANK
3
2
BANK12, 1
3
BANK14,22
BANK2
3
,24
BANK112,11
3
BANK24
BANK
3
4
BANK
3
2
BANK
33
BANK116
BANK
33
BANK
3
4
BANK15,16
BANK
3
4,116
BANK0
BANK24,
3
4
BANK14
BANK114
BANK115
BANK24
BANK14,
33
,
3
6
BANK 25,
3
5
BANK 26,
3
6
