Xilinx ML605 User Manual Download

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ML605 Hardware User Guide

UG534

(v1.2.1) January 21, 2010

Chapter 1:

ML605 Evaluation Board

E24

DDR3_D54

174

DQ54

G25

DDR3_D55

176

DQ55

F28

DDR3_D56

181

DQ56

B31

DDR3_D57

183

DQ57

H29

DDR3_D58

191

DQ58

H28

DDR3_D59

193

DQ59

B30

DDR3_D60

180

DQ60

A30

DDR3_D61

182

DQ61

E29

DDR3_D62

192

DQ62

F29

DDR3_D63

194

DQ63

E11

DDR3_DM0

DM0

B11

DDR3_DM1

DM1

E14

DDR3_DM2

DM2

D19

DDR3_DM3

DM3

B22

DDR3_DM4

136

DM4

A26

DDR3_DM5

153

DM5

A29

DDR3_DM6

170

DM6

A31

DDR3_DM7

187

DM7

E12

DDR3_DQS0_N

DQS0_N

D12

DDR3_DQS0_P

DQS0_P

J12

DDR3_DQS1_N

DQS1_N

H12

DDR3_DQS1_P

DQS1_P

A14

DDR3_DQS2_N

DQS2_N

A13

DDR3_DQS2_P

DQS2_P

H20

DDR3_DQS3_N

DQS3_N

H19

DDR3_DQS3_P

DQS3_P

C23

DDR3_DQS4_N

135

DQS4_N

B23

DDR3_DQS4_P

137

DQS4_P

A25

DDR3_DQS5_N

152

DQS5_N

B25

DDR3_DQS5_P

154

DQS5_P

G28

DDR3_DQS6_N

169

DQS6_N

H27

DDR3_DQS6_P

171

DQS6_P

D30

DDR3_DQS7_N

186

DQS7_N

Table 1-4:

DDR3 SODIMM Connections

(Cont’d)

U1 FPGA Pin

Schematic Net Name

J1 SODIMM

Pin Number

Pin Name

Summary of Contents for ML605

Page 1: ...User Guide optional UG534 v1 2 1 January 21 2010 optional ML605 Hardware User Guide UG534 v1 2 1 January 21 2010...

Page 2: ...XPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE...

Page 3: ...ACE CF and CompactFlash Connector 24 6 USB JTAG 26 7 Clock Generation 27 Oscillator Differential 27 Oscillator Socket Single Ended 2 5V 27 SMA Connectors Differential 29 8 Multi Gigabit Transceivers...

Page 4: ...Enable Boot EEPROM Select and Addr Select DIP Switch S2 56 19 VITA 57 1 FMC HPC Connector 57 20 VITA 57 1 FMC LPC Connector 63 21 Power Management 65 AC Adapter and Input Power Jack Switch 65 Onboard...

Page 5: ...Virtex 6 Family Overview The features and product selection of the Virtex 6 family are outlined in this overview Virtex 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the...

Page 6: ...Tri Mode Ethernet Media Access Controller available in all Virtex 6 FPGAs except the XC6VLX760 Virtex 6 FPGA DSP48E1 Slice User Guide This guide describes the architecture of the DSP48E1 slice in Vir...

Page 7: ...on page 11 Additional Information Additional information and support material is located at http www xilinx com ml605 This information includes Current version of this user guide in PDF format Example...

Page 8: ...cillator differential Socketed 2 5V oscillator single ended SMA connectors differential SMA connectors for MGT clocking 8 Multi Gigabit Transceivers GTX MGTs FMC HPC connector FMC LPC connector SMA PC...

Page 9: ...SMA GPIO connectors 2 LCD character display 16 characters x 2 lines 18 Switches Power on off slide switch System ACE CF reset pushbutton System ACE CF bitstream image select DIP switch Configuration...

Page 10: ...cuit VITA 57 1 FMC HPC Connector VITA 57 1 FMC LPC Connector Virtex 6 FPGA XC6VLX240T 1FFG1156 System ACE CF S A CompactFlash S A 8 bit MPU I F User LED SW User DIP SW User LCD 200 MHz LVDS Clock SMA...

Page 11: ...05 Board Photo 1 2 8 13 5 10 15 8 13 16b 16c 23 19 18a 18b 18c 18d 7c 17e 17c 17b 17f 21a 21a 21b 21c 21d 22 7a on backside 7b 17a 17d 20 12 6 16a 7d 11 14 3 4 9 UG534_02_123009 Table 1 1 ML605 Featur...

Page 12: ...bs CP2103GM bridge 33 13 USB A Host USB Mini B peripheral connectors Cypress CY7C67300 100AXI controller 27 14 Video DVI connector Chrontel CH7301C TF Video codec 28 29 15 IIC NV EEPROM 8 Kb on backsi...

Page 13: ...using System ACE CF and CompactFlash card 18 Switches 13 25 39 a Power On Off Slide switch 39 b FPGA_PROG_B pushbutton active Low 13 c System ACE CF Image Select 4 pole DIP switch active High 25 d Mo...

Page 14: ...le 1 2 Virtex 6 FPGA Configuration Modes Configuration Mode M 2 0 Bus Width 1 CCLK Direction Master Serial 2 000 1 Output Master SPI 2 001 1 Output Master BPI Up 2 010 8 16 Output Master BPI Down 2 01...

Page 15: ...ding DCI between adjacent banks as follows CONFIG DCI_CASCADE 36 35 CONFIG DCI_CASCADE 26 25 Table 1 4 shows the connections and pin numbers for the DDR3 SODIMM Bank 24 VCC2V5_FPGA 2 5V Bank 25 VCC1V5...

Page 16: ...DR3_BA1 108 BA1 L15 DDR3_BA2 79 BA2 J11 DDR3_D0 5 DQ0 E13 DDR3_D1 7 DQ1 F13 DDR3_D2 15 DQ2 K11 DDR3_D3 17 DQ3 L11 DDR3_D4 4 DQ4 K13 DDR3_D5 6 DQ5 K12 DDR3_D6 16 DQ6 D11 DDR3_D7 18 DQ7 M13 DDR3_D8 21 D...

Page 17: ...2 B21 DDR3_D33 131 DQ33 A23 DDR3_D34 141 DQ34 A24 DDR3_D35 143 DQ35 C20 DDR3_D36 130 DQ36 D20 DDR3_D37 132 DQ37 J20 DDR3_D38 140 DQ38 G22 DDR3_D39 142 DQ39 D26 DDR3_D40 147 DQ40 F26 DDR3_D41 149 DQ41...

Page 18: ..._DM3 63 DM3 B22 DDR3_DM4 136 DM4 A26 DDR3_DM5 153 DM5 A29 DDR3_DM6 170 DM6 A31 DDR3_DM7 187 DM7 E12 DDR3_DQS0_N 10 DQS0_N D12 DDR3_DQS0_P 12 DQS0_P J12 DDR3_DQS1_N 27 DQS1_N H12 DDR3_DQS1_P 29 DQS1_P...

Page 19: ...ences See the Micron Technology Inc for more information Ref 22 In addition see the Virtex 6 FPGA Memory Interface Solutions User Guide Ref 6 and the Virtex 6 FPGA Memory Resources User Guide Ref 9 C3...

Page 20: ...PI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL The P30_CS net is used to select the P30 or the XCF128 Power on configuration is selected by the P30_CS ne...

Page 21: ...switched by S2 switch 6 which allows the lower or upper half of U4 to be chosen as a data source Table 1 5 shows the connections and pin numbers for the boot flash devices Table 1 5 Platform Flash and...

Page 22: ...13 50 DQ13 H5 DQ13 L24 FLASH_D14 52 DQ14 G7 DQ14 M23 FLASH_D15 54 DQ15 E7 DQ15 J26 FLASH_WAIT 56 WAIT NA 1 NA 1 AF23 FPGA_FWE_B 14 WE G8 W AA24 FPGA_FOE_B 32 OE F8 G K8 FPGA_CCLK NA 1 NA 1 F1 K AC23 P...

Page 23: ...connect the FPGA design or EDK embedded memory controller EMC peripheral to the flash through the pins defined in Table 1 5 page 21 The Platform Flash XL defaults to a synchronous read mode Typically...

Page 24: ...iant to the DOS 8 3 short file name format This means that the folder names can be up to eight characters long and cannot contain the following reserved characters This DOS 8 3 file name restriction d...

Page 25: ...YSACE_D3 62 MPD03 AG16 SYSACE_D4 61 MPD04 AH15 SYSACE_D5 60 MPD05 AF16 SYSACE_D6 59 MPD06 AN15 SYSACE_D7 58 MPD07 AC15 SYSACE_MPA00 70 MPA00 AP15 SYSACE_MPA01 69 MPA01 AG17 SYSACE_MPA02 68 MPA02 AH17...

Page 26: ...gure 1 5 and Figure 1 6 When either or both VITA 57 1 FMC expansion connectors are populated with an expansion module that has a JTAG chain the respective jumper s must be set to connect pins 2 3 in o...

Page 27: ...porary design in the FPGA iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22 connector For an overview on configuring the FPGA see Configuration Options page 73...

Page 28: ...Guide UG534 v1 2 1 January 21 2010 Chapter 1 ML605 Evaluation Board X Ref Target Figure 1 7 Figure 1 7 ML605 Oscillator Socket Pin 1 Location Identifiers Silkscreened outline has beveled corner UG534_...

Page 29: ...al A high precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50 ohm SMA connectors J58 P J55 N X Ref Target Figure 1 8 Figure 1 8 ML605 Oscillator...

Page 30: ...X Ref Target Figure 1 9 Figure 1 9 GTX SMA Clock UG534_09_081309 SMA_REFCLK_C_N1 J30 32K10K 400E3 J31 32K10K 400E3 SMA_REFCLK_N SMA_REFCLK_P SMA_REFCLK_C_P1 GND1 GND2 GND3 GND4 SIG SIG GND5 GND6 GND7...

Page 31: ...Ie Fingers HCSL 250 MHz LVDS GTX_X0Y19 GTX_X0Y18 GTX_X0Y17 GTX_X0Y16 GTX_X0Y15 GTX_X0Y14 GTX_X0Y13 GTX_X0Y12 GTX_X0Y11 GTX_X0Y10 GTX_X0Y09 GTX_X0Y08 GTX_X0Y07 GTX_X0Y06 GTX_X0Y05 GTX_X0Y04 GTX_X0Y03 G...

Page 32: ...ize is selected via jumper J42 as shown in Figure 1 12 The default lane size selection is 1 lane J42 pins 1 and 2 jumpered X Ref Target Figure 1 11 Figure 1 11 PCIe MGT Banks 114 and 115 Clocking UG53...

Page 33: ...nt block transmit pair GTXE1_X0Y10 P2 PCIE_TX4_N A36 PERn4 T1 PCIE_TX5_P A39 PERp5 Integrated Endpoint block transmit pair GTXE1_X0Y9 T2 PCIE_TX5_N A40 PERn5 V1 PCIE_TX6_P A43 PERp6 Integrated Endpoin...

Page 34: ...r connect an auxiliary PCIe 6 pin molex power connector to J60 6 pin molex on the ML605 board as this could result in damage to the PCIe motherboard and or ML605 board The 6 pin molex connector is mar...

Page 35: ...The SFP interface is connected to MGT Bank 116 on the FPGA The SFP module serial ID interface is connected to the SFP IIC bus see 15 IIC Bus page 42 for more information The control and status signals...

Page 36: ...odule Connector Pin Number Pin Name E3 SFP_RX_P 13 RDP_13 E4 SFP_RX_N 12 RDN_12 C3 SFP_TX_P 18 TDP_18 C4 SFP_TX_N 19 TDN_19 V23 SFP_LOS 8 LOS AP12 SFP_TX_DISABLE 1 3 TX_DISABLE Notes 1 The SFP TX Disa...

Page 37: ...it 2 Definition and Value Bit 1 Definition and Value Bit 0 Definition and Value X Ref Target Figure 1 13 Figure 1 13 Ethernet SGMII Clock 125 MHz VDDA_SGMIICLK ICS84402II VDDA VDD VDD_SGMIICLK SGMIICL...

Page 38: ...PHY_RXD6 121 RXD6 AC13 PHY_RXD7 120 RXD7 AH12 PHY_TXC_GTXCLK 14 GTXCLK AD12 PHY_TXCLK 10 TXCLK AH10 PHY_TXER 13 TXER AJ10 PHY_TXCTL_TXEN 16 TXEN AM11 PHY_TXD0 18 TXD0 AL11 PHY_TXD1 19 TXD1 AG10 PHY_T...

Page 39: ...driver must be installed on the host PC prior to establishing communications with the ML605 Refer to the evaluation kit Getting Started Guide for driver installation instructions References Refer to t...

Page 40: ...heral Controller EPC v1 02a Data Sheet for more information Ref 20 Table 1 16 USB Controller Connections U1 FPGA Pin Schematic Net Name U81 USB Controller Pin Number Pin Name Y32 USB_A0_LS 52 GPIO19_A...

Page 41: ...way of the video IIC bus The DVI connector Table 1 17 supports the IIC protocol to allow the board to read the monitor s configuration parameters These parameters can be read by the FPGA using the DV...

Page 42: ...ank 34 MAIN IIC interface 8Kb NV Memory U6 FMC HPC connector J64 DDR3 SODIMM Socket J1 The DVI IIC bus hosts two items FPGA U1 Bank 34 DVI IIC interface DVI codec U38 and DVI connector J63 The LPC IIC...

Page 43: ...T MICRO M24C08 WDW6TP FMC HPC COLUMN C 2 Kb EEPROM on any FMC LPC Mezzanine Card DDR3 SODIMM SOCKET P4 SFP MODULE CONNECTOR IIC_SDA_MAIN SFP_MOD_DEF2 SFP_MOD_DEF1 IIC_SDA_DVI_F BANK 13 BANK 34 BANK 33...

Page 44: ...the Xilinx XPS IIC Bus Interface v2 00a Data Sheet Ref 21 X Ref Target Figure 1 15 Figure 1 15 IIC Memory U6 UG534_15_072109 IIC SCL MAIN VCC3V3 VCC3V3 VCC3V3 IIC Address 0b1010100 IIC SDA MAIN U6 SCL...

Page 45: ...UCD9240 controllers report power good DS13 FPGA_DONE GREEN DONE FPGA configured successfully DS23 LED_GRN GREEN STATUS USB JTAG Connection Status Dual LED LED_RED RED DS25 12V GREEN 12V 12V Power On D...

Page 46: ...to a PC motherboard They are mounted in right angle plastic housings and can be seen on the connector end of the board This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2 X Ref...

Page 47: ...5 provides the following user and general purpose I O capabilities User LEDs 8 with parallel wired GPIO male pin header User Pushbutton 5 switches with associated direction LEDs CPU Reset pushbutton s...

Page 48: ...R17 27 4 1 1 16W R16 27 4 1 1 16W R15 27 4 1 1 16W R14 27 4 1 1 16W R13 27 4 1 1 16W R11 27 4 1 1 16W R10 27 4 1 1 16W R9 27 4 1 1 16W R8 27 4 1 1 16W R7 27 4 1 1 16W R6 27 4 1 1 16W R5 27 4 1 1 16W 1...

Page 49: ...re assigned as GPIO and the sixth is assigned as CPU_RESET Figure 1 19 and Table 1 22 page 50 describe the pushbutton switches Table 1 21 User LED Connections FPGA U1 Pin Schematic Net Name GPIO J62 P...

Page 50: ...W10 2 X Ref Target Figure 1 20 Figure 1 20 User 8 pole DIP Switch UG534_20_072109 GPIO DIP SW1 GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SW4 GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8 1 2 3 4 5 6 7...

Page 51: ...1 21 and Table 1 24 X Ref Target Figure 1 21 Figure 1 21 User SMA GPIO UG534_21_072109 USER SMA GPIO N J56 32K10K 400E3 J76 32K10K 400E3 GND1 SIG 1 1 SIG GND2 GND3 GND4 GND5 GND6 GND7 GND1 GND2 GND3 G...

Page 52: ...mode only The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it Caution Care should be taken not to scratch or damage the surface of the...

Page 53: ...he onboard power system X Ref Target Figure 1 23 Figure 1 23 Power On Off Slide Switch SW2 UG534_23 _081209 N C 12v 12v N C COM COM 1 4 2 3 6 1 2 3 4 5 NC NC 39 30 1060 ATX Peripheral Cable Connector...

Page 54: ...e pin is high enabled by closing DIP switch S1 switch 4 the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed See 5...

Page 55: ...nd CompactFlash Connector page 24 for more details about the System ACE controller Note S1 switch 4 is the System ACE controller enable switch When ON this switch allows the System ACE to boot at powe...

Page 56: ...lect S2 switch 6 is used to select the upper or lower half of flash memory U4 as the source of the FPGA bitstream image When FLASH_A23 is High the upper half of the address is selected When FLASH_A23...

Page 57: ...differential user defined signals 10 MGTs 2 MGT clocks 4 differential clocks 159 ground 15 power connections Of the above signal and clock connectivity capability the ML605 implements the following su...

Page 58: ...2C_N AE4 B13 FMC_HPC_DP7_M2C_N AP6 A6 FMC_HPC_DP2_M2C_P AF5 B16 FMC_HPC_DP6_M2C_P AM5 A7 FMC_HPC_DP2_M2C_N AF6 B17 FMC_HPC_DP6_M2C_N AM6 A10 FMC_HPC_DP3_M2C_P AG3 B20 FMC_HPC_GBTCLK1_M2C_P AK6 A11 FMC...

Page 59: ...PC_PG_M2C_LS 1 J27 E3 FMC_HPC_HA01_CC_N AC29 F4 FMC_HPC_HA00_CC_P AE33 E6 FMC_HPC_HA05_P AB27 F5 FMC_HPC_HA00_CC_N AF33 E7 FMC_HPC_HA05_N AC27 F7 FMC_HPC_HA04_P AB28 E9 FMC_HPC_HA09_P AB30 F8 FMC_HPC_...

Page 60: ...MC_HPC_LA07_P AK21 G15 FMC_HPC_LA12_P AM21 H14 FMC_HPC_LA07_N AJ21 G16 FMC_HPC_LA12_N AL21 H16 FMC_HPC_LA11_P AM22 G18 FMC_HPC_LA16_P AP22 H17 FMC_HPC_LA11_N AN22 G19 FMC_HPC_LA16_N AN23 H19 FMC_HPC_L...

Page 61: ...M32 K26 FMC_HPC_HB00_CC_N AG30 J27 FMC_HPC_HB07_P AJ34 K28 FMC_HPC_HB06_CC_P AF26 J28 FMC_HPC_HB07_N AH34 K29 FMC_HPC_HB06_CC_N AE26 J30 FMC_HPC_HB11_P AJ29 K31 FMC_HPC_HB10_P AF28 J31 FMC_HPC_HB11_N...

Page 62: ...ly Voltages for HPC Connector Voltage Supply Allowable Voltage Range No Pins Max Amps Tolerance Max Capacitive Load VADJ Fixed 2 5V 4 4 5 1000 uF VIO_B_M2C 0 VADJ 2 1 15 5 500 uF VREF_A_M2C 0 VADJ 1 1...

Page 63: ...defined signals 1 MGT 1 MGT clock 2 differential clocks 61 ground 10 power connections Of the above signal and clock connectivity capability the ML605 implements the full set 34 differential user def...

Page 64: ...14 FMC_LPC_LA10_P F30 D14 FMC_LPC_LA09_P L25 C15 FMC_LPC_LA10_N G30 D15 FMC_LPC_LA09_N L26 C18 FMC_LPC_LA14_P C33 D17 FMC_LPC_LA13_P D34 C19 FMC_LPC_LA14_N B34 D18 FMC_LPC_LA13_N C34 C22 FMC_LPC_LA18_...

Page 65: ...plug a PC ATX power supply 6 pin connector into ML605 connector J60 The ATX 6 pin connector has a different pinout than ML605 J60 and connecting the ATX 6 pin connector will damage the ML605 and void...

Page 66: ...wer Controller 2 UCD9240PFC U25 Switching Regulator UCD7230RG 1 00V 6A max U35 Switching Regulator UCD7230RG 1 20V 6A max U36 Switching Module PTD08A010W 1 5V 10A max U20 Switching Module PTD08A010W 3...

Page 67: ...Description Power Rail Net Name Power Rail Voltage Schematic Page UCD9240PFC U24 PMBus Controller Core Addr 52 35 PTD08A020W U42 20A 0 6V 3 6V Adj Switching Regulator VCCINT_FPGA 1 00V 36 PTD08A020W U...

Page 68: ...pply pins and supports the use of an external 1 25V reference IC U23 for the analog to digital conversion process An option using jumper J19 to select an on chip reference is also provided however the...

Page 69: ...hunt in the FPGA 1V Vccint core supply are also available on this header By connecting header pins 9 to 11 and 10 to 12 using jumpers the system monitor can be used to monitor the FPGA core current an...

Page 70: ...ed to monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier InAmp The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24 0 5V The...

Page 71: ...connect at header J59 as shown in Figure 1 32 The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed Alternatively the FPGA te...

Page 72: ...inal to provide information on the FPGA power supplies temperature and power consumption In addition the UART interface can be used to margin the FPGA supplies over the PMBus The System Monitor functi...

Page 73: ...socket U73 System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1 With no CF card present the ML605 can be configured via the onboard J...

Page 74: ...74 www xilinx com ML605 Hardware User Guide UG534 v1 2 1 January 21 2010 Chapter 1 ML605 Evaluation Board...

Page 75: ...4 SysACE Mode 1 1 off 3 SysAce CFGAddr 2 0 off 2 SysAce CFGAddr 1 0 off 1 SysAce CFGAddr 0 0 off S2 FPGA mode boot PROM select and FPGA CCLK select 6 pole DIP switch 6 FLASH_A23 0 off 5 M2 0 off 4 M1...

Page 76: ...2 3 SGMII to Cu no clk Jump 1 2 J67 pins 1 2 GMII MII to Cu pins 2 3 SGMII to Cu no clk Jump 1 2 J68 J66 pins 1 2 J68 ON RGMII modified MII in Cu no jumper FMC Bypass J18 exclude FMC LPC connector Jum...

Page 77: ...09_P LA10_P NC NC 15 NC NC GND LA12_P NC NC LA09_N LA10_N NC NC 16 NC NC LA11_P LA12_N NC NC GND GND NC NC 17 NC NC LA11_N GND NC NC LA13_P GND NC NC 18 NC NC GND LA16_P NC NC LA13_N LA14_P NC NC 19 N...

Page 78: ...6_M2C_P G ND 17 HA17_N_C C G ND LA11_N GND HA15_N GND LA13_P GND DP6_M2C _N GND 18 G ND HA18_P GND LA16_P GND HA20_P LA13_N LA14_P GND DP5_M2C _P 19 HA21_P HA18_N LA15_P LA16_N HA19_P HA20_N GND LA14_...

Page 79: ...3 on U19 NET CPU_RESET LOC H10 2 on SW10 pushbutton active High NET DDR3_A0 LOC L14 98 on J1 NET DDR3_A1 LOC A16 97 on J1 NET DDR3_A2 LOC B16 96 on J1 NET DDR3_A3 LOC E16 95 on J1 NET DDR3_A4 LOC D16...

Page 80: ...ET DDR3_D36 LOC C20 130 on J1 NET DDR3_D37 LOC D20 132 on J1 NET DDR3_D38 LOC J20 140 on J1 NET DDR3_D39 LOC G22 142 on J1 NET DDR3_D40 LOC D26 147 on J1 NET DDR3_D41 LOC F26 149 on J1 NET DDR3_D42 LO...

Page 81: ...54 on U38 thru series R104 47 5 ohm NET DVI_D8 LOC AE18 53 on U38 thru series R103 47 5 ohm NET DVI_D9 LOC AF18 52 on U38 thru series R102 47 5 ohm NET DVI_D10 LOC AL16 51 on U38 thru series R101 47 5...

Page 82: ...and switch S2 2 setting select either U4 or U27 NET FMC_HPC_CLK0_M2C_N LOC K23 H5 on J64 NET FMC_HPC_CLK0_M2C_P LOC K24 H4 on J64 NET FMC_HPC_CLK1_M2C_N LOC AP21 G3 on J64 NET FMC_HPC_CLK1_M2C_P LOC...

Page 83: ...C AB31 E10 on J64 NET FMC_HPC_HA09_P LOC AB30 E9 on J64 NET FMC_HPC_HA10_N LOC AC34 K14 on J64 NET FMC_HPC_HA10_P LOC AD34 K13 on J64 NET FMC_HPC_HA11_N LOC AG32 J13 on J64 NET FMC_HPC_HA11_P LOC AG33...

Page 84: ...C AG27 K37 on J64 NET FMC_HPC_HB18_N LOC AD26 J37 on J64 NET FMC_HPC_HB18_P LOC AD25 J36 on J64 NET FMC_HPC_HB19_N LOC AK31 E34 on J64 NET FMC_HPC_HB19_P LOC AL31 E33 on J64 NET FMC_HPC_LA00_CC_N LOC...

Page 85: ...C AK24 H35 on J64 NET FMC_HPC_LA30_P LOC AJ24 H34 on J64 NET FMC_HPC_LA31_N LOC AK29 G34 on J64 NET FMC_HPC_LA31_P LOC AL29 G33 on J64 NET FMC_HPC_LA32_N LOC AG26 H38 on J64 NET FMC_HPC_LA32_P LOC AG2...

Page 86: ...J63 NET FMC_LPC_LA21_N LOC T26 H26 on J63 NET FMC_LPC_LA21_P LOC R26 H25 on J63 NET FMC_LPC_LA22_N LOC P27 G25 on J63 NET FMC_LPC_LA22_P LOC N27 G24 on J63 NET FMC_LPC_LA23_N LOC R27 D24 on J63 NET FM...

Page 87: ...AE24 2 on LED DS22 7 on J62 NET GPIO_LED_7 LOC AD24 2 on LED DS21 8 on J62 NET GPIO_LED_C LOC AP24 2 on LED DS16 NET GPIO_LED_E LOC AE21 2 on LED DS19 NET GPIO_LED_N LOC AH27 2 on LED DS20 NET GPIO_L...

Page 88: ...PCIE_TX7_P LOC Y1 A47 on P1 NET PCIE_WAKE_B_LS LOC AD22 B11 on P1 NET PHY_COL LOC AK13 114 on U80 NET PHY_CRS LOC AL13 115 on U80 NET PHY_INT LOC AH14 32 on U80 NET PHY_MDC LOC AP14 35 on U80 NET PHY_...

Page 89: ...T SYSACE_D1 LOC AJ17 65 on U19 NET SYSACE_D2 LOC AJ16 63 on U19 NET SYSACE_D3 LOC AP16 62 on U19 NET SYSACE_D4 LOC AG16 61 on U19 NET SYSACE_D5 LOC AH15 60 on U19 NET SYSACE_D6 LOC AF16 59 on U19 NET...

Page 90: ...LOC Y33 16 on U30 NET USB_D15_LS LOC Y31 6 on U30 NET USB_INT_LS LOC Y27 6 on U29 NET USB_RD_B_LS LOC W25 16 on U29 NET USB_RESET_B_LS LOC T25 8 on U30 NET USB_WR_B_LS LOC V25 4 on U29 NET USER_CLOCK...

Page 91: ...6 FPGA SelectIO Resources User Guide 8 UG362 Virtex 6 FPGA User Guide Clocking Resources 9 UG363 Virtex 6 FPGA Memory Resources User Guide 10 UG364 Virtex 6 FPGA Configurable Logic Block User Guide 11...

Page 92: ...25Q64VSFIG 24 Numonyx Embedded Flash Memory Data Sheet TE28F128J3D 75 25 Epson Toyocom Oscillator Data Sheet EG 2121CA 200 0000M LHPA 26 MMD Components MBH Series Data Sheet MBH2100H 66 000 MHz 27 PCI...

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