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www.xilinx.com
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Chapter 1:
ML505/ML506/ML507 Evaluation Platform
R
Block Diagram
Figure 1-1
shows a block diagram of the ML50
x
Evaluation Platform (board).
Related Xilinx Documents
Prior to using the ML50
x
Evaluation Platform, users should be familiar with Xilinx
resources. See
Appendix C, “References”
for direct links to Xilinx documentation. See the
following locations for additional documentation on Xilinx tools and solutions:
•
EDK:
www.xilinx.com/edk
•
ISE:
www.xilinx.com/ise
•
Answer Browser:
www.xilinx.com/support
•
Intellectual Property:
www.xilinx.com/ipcenter
Figure 1-1:
Virtex-5 FPGA ML50
x
Evaluation Platform Block Diagram
Virtex-5
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