ML505/ML506/ML507 Evaluation Platform
www.xilinx.com
7
UG347 (v3.1.1) October 7, 2009
R
Preface
About This Guide
The ML50
x
evaluation platforms enable designers to investigate and experiment with
features of Virtex®-5 FPGAs. This user guide describes the features and operation of the
ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.
Guide Contents
This manual contains the following chapters:
•
Chapter 1, “ML505/ML506/ML507 Evaluation Platform,”
provides details on the
board components
•
Appendix A, “Board Revisions,”
details the differences between board revisions
•
Appendix B, “Programming the IDT Clock Chip,”
shows how to restore the default
factory settings for the clock chip on the ML50
x
boards
•
Appendix C, “References”
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5
.
•
Virtex-5 FPGA Family Overview
The features and product selection of the Virtex-5 FPGA family are outlined in this
overview.
•
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 FPGA family.
•
Virtex-5 FPGA User Guide
This user guide includes chapters on:
♦
Clocking Resources
♦
Clock Management Technology (CMT)
♦
Phase-Locked Loops (PLLs)
♦
Block RAM and FIFO memory
♦
Configurable Logic Blocks (CLBs)
♦
SelectIO™ Resources
♦
I/O Logic Resources
♦
Advanced I/O Logic Resources
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