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Xilinx ML505, User Manual

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48

www.xilinx.com

ML505/ML506/ML507 Evaluation Platform

UG347 (v3.1.1) October 7, 2009

Chapter 1:

ML505/ML506/ML507 Evaluation Platform

R

44. Soft Touch Landing Pad

An Agilent Pro Series soft touch landing pad is available for use with a logic analyzer. The 
landing pad is designed for use with the Agilent E5404/06A 34-channel single-ended 
probe. The soft touch landing pad shares some pins with the XGI header. Signals that the 
user wants to probe can be connected to header pin signals specified in 

Table 1-33

. For 

more information about soft touch connectors, see 

www.agilent.com/find/softtouch

.

Table 1-33:

Landing Pad Signals on XGI Header

Pad Number

Header Pin

FPGA Pin

A1

HDR1_2

H33

A2

HDR1_4

F34

A3

GND

N/A

A4

HDR1_10

G32

A5

HDR1_12

H32

A6

GND

N/A

A7

HDR2_36_SM_15_P

W34

A8

HDR2_34_SM_15_N

V34

A9

GND

N/A

A10

HDR1_22

P34

A11

HDR1_24

N34

A12

GND

N/A

A13

HDR1_30

Y34

A14

HDR1_32

Y32

A15

GND

N/A

A16

HDR1_38

AE32

A17

HDR1_40

AG32

A18

GND

N/A

A19

HDR1_46

AK33

A20

HDR1_48

AJ32

A21

GND

N/A

A22

HDR1_50

AK32

A23

HDR1_52

AL34

A24

GND

N/A

A25

HDR1_58

AJ34

A26

HDR1_60

AM32

A27

GND

N/A

B1

GND

N/A

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Summary of Contents for ML505

Page 1: ...07 Evaluation Platform User Guide optional UG347 v3 1 1 October 7 2009 optional ML505 ML506 ML507 Evaluation Platform User Guide UG347 v3 1 1 October 7 2009 Downloaded from Elcodis com electronic comp...

Page 2: ...OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2006 2009 Xilinx Inc All rights reserved XILINX the Xilinx logo the Brand Window and other designated brands included herein are trademarks...

Page 3: ...dix C References 07 21 08 3 0 1 Updated link in Appendix C References Updated Appendix A Board Revisions 11 10 08 3 1 Added content to 17 System ACE and CompactFlash Connector page 28 and Configuratio...

Page 4: ...ML505 ML506 ML507 Evaluation Platform www xilinx com UG347 v3 1 1 October 7 2009 Downloaded from Elcodis com electronic components distributor...

Page 5: ...and Contrast Adjustment 20 6 GPIO DIP Switches Active High 20 7 User and Error LEDs Active High 21 8 User Pushbuttons Active High 22 9 CPU Reset Button Active Low 22 10 XGI Expansion Headers 22 Diffe...

Page 6: ...P GTX Input and Output with SMA Connectors 42 40 PCI Express Interface 43 41 Serial ATA Host Connectors 44 42 SFP Connector 44 43 GTP GTX Clocking Circuitry 46 Overview 46 Frequency Synthesizer for SF...

Page 7: ...tore the default factory settings for the clock chip on the ML50x boards Appendix C References Additional Documentation The following documents are also available for download at http www xilinx com v...

Page 8: ...am encryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces Virtex 5 FPGA System Monitor User Guide The System Monitor function...

Page 9: ...se Example Blue text Cross reference link to a location in the current document See the section Additional Documentation for details Red text Cross reference link to a location in another document See...

Page 10: ...10 www xilinx com ML505 ML506 ML507 Evaluation Platform UG347 v3 1 1 October 7 2009 Preface About This Guide R Downloaded from Elcodis com electronic components distributor...

Page 11: ...G1136 ML505 XC5VSX50T 1FFG1136 ML506 XC5VFX70T 1FFG1136 ML507 Two Xilinx XCF32P Platform Flash PROMs 32 Mb each for storing large device configurations Xilinx System ACE CompactFlash configuration con...

Page 12: ...45 with support for MII GMII RGMII and SGMII Ethernet PHY interfaces USB interface chip with host and peripheral ports Rechargeable lithium battery to hold FPGA encryption keys JTAG configuration por...

Page 13: ...System ACE controller Platform Flash PROM configuration storage device CPLD and linear flash chips MicroBlaze EDK reference design files Full schematics in PDF format and ViewDraw schematic format PC...

Page 14: ...1 Virtex 5 FPGA ML50x Evaluation Platform Block Diagram Virtex 5 LXT SXT FXT FPGA UG347_03_110807 GPIO Button LED DIP Switch PLL Clock Generator Plus User Oscillator System Monitor SMA Differential I...

Page 15: ...16 back The numbered sections on the pages following the figures contain details on each feature Figure 1 2 Detailed Description of Virtex 5 FPGA ML505 Components Front 1 4 39 34 UG347_01_102907 8 5 2...

Page 16: ...ML506 ML507 Evaluation Platform R Note The label on the CompactFlash CF card shipped with your board might differ from the one shown Figure 1 3 Detailed Description of Virtex 5 FPGA ML505 Components...

Page 17: ...ch bank Table 1 1 I O Voltage Rail of FPGA Banks FPGA Bank I O Voltage Rail 0 3 3V 1 3 3V 2 3 3V 3 2 5V no DCI 4 3 3V no DCI 5 1 3 3V DCI with 49 9 resistors installed 6 3 3V unused 11 User selectable...

Page 18: ...the requirements defined by the MIG User Guide using the MIG tool The MIG documentation requires that designers follow the MIG pinout and layout guidelines The MIG tool generates and ensures that the...

Page 19: ...directly feed the global clock input pins of the FPGA The FPGA can be configured to present a 100 termination impedance A differential clock output from the FPGA is driven out through an LVDS clock mu...

Page 20: ...hip 5 LCD Brightness and Contrast Adjustment Turning potentiometer R87 adjusts the image contrast of the character LCD The potentiometer should be turned with a screwdriver 6 GPIO DIP Switches Active...

Page 21: ...hrough the CPLD to allow the LED signals to be used as higher performance I O by way of the XGI expansion connector Table 1 6 summarizes the LED definitions and connections Table 1 6 User and Error LE...

Page 22: ...ground 2 5V 3 3V 5V power JTAG chain and the IIC bus All signals on connectors J4 and J6 have matched length traces that are matched to each other Differential Expansion I O Connectors Header J4 cont...

Page 23: ...Schematic Net Name FPGA Pin Pos Neg Pos Neg Pos Neg 4 2 HDR2_4 HDR2_2 L34 K34 8 6 HDR2_8 HDR2_6 K33 K32 12 10 HDR2_12 HDR2_10 P32 N32 16 14 HDR2_16 HDR2_14 T33 R34 20 18 HDR2_20 HDR2_18 R33 R32 24 22...

Page 24: ...he board The expansion connector also allows the board s JTAG chain to be extended onto the expansion card by setting jumper J21 accordingly The IIC bus on the board is also extended onto the expansio...

Page 25: ...atform Table 1 11 summarizes the additional expansion I O connections Table 1 11 Additional Expansion I O Connections J5 J5 Pin Label FPGA Pin Description 1 VCC5 5V Power Supply 2 VCC5 5V Power Supply...

Page 26: ...e jack is driven by the audio codec s internal 50 mW amplifier The SPDIF jack supplies digital audio output from the codec Table 1 12 summarizes the audio jacks Table 1 13 shows the control pins for t...

Page 27: ...s used to shift the voltage level between the FPGA and the LCD The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it Caution Care should...

Page 28: ...that the power load of any attached PS 2 devices does not overload the AC adapter 17 System ACE and CompactFlash Connector The Xilinx System ACE CompactFlash CF configuration controller allows a Type...

Page 29: ...ore the original demonstration image are available online ML505 http www xilinx com products boards ml505 images htm ML506 http www xilinx com products boards ml506 images htm ML507 http www xilinx co...

Page 30: ...ur parity bits The ZBT SRAM is located under the removable LCD and is not visible in Figure 1 2 page 15 Note The SRAM and FLASH memory share the same data bus 19 Linear Flash Chips A NOR linear flash...

Page 31: ...des are selectable by the jumpers as shown in Table 1 15 Table 1 15 Board Connections for PHY Configuration Pins Config Pin Connection on Board Bit 2 Definition and Value Bit 1 Definition and Value Bi...

Page 32: ...through an RS 232 transceiver to assist with debug Jumper J50 can be installed to prevent the USB controller from executing firmware stored in the IIC EEPROM 23 Xilinx XCF32P Platform Flash PROM Confi...

Page 33: ...guration Options page 53 section for more information 25 Onboard Power Supplies Power supply circuitry on the board generates 0 9V 1 0V 1 8V 2 5V and 3 3V voltages to power the components on the board...

Page 34: ...or better than 10 The power switch SW1 turns the board on and off by controlling the 5V supply to the board as shown in Figure 1 5 page 34 Note Never apply power to the power brick connector P20 and t...

Page 35: ...position DIP switch SW3 sets the address and mode of configuration It also enables fallback configuration of the Platform Flash PROM and enables System ACE configuration Table 1 17 lists the function...

Page 36: ...lash ST Microelectronics M25P32 The SPI Flash can be used for FPGA configuration or to hold user data The SPI Flash can be in system programmed using a Xilinx download cable with flying leads attached...

Page 37: ...be accommodated on the board The board does not ship with a heatsink fan unit but can accommodate one for example Calgreg Electronics Smart CLIP family of heatsink fan assemblies 35 Piezo A piezo aud...

Page 38: ...lable through the CPU JTAG port J51 providing the appropriate connections to the FPGA fabric are in place VGA_IN_RED5 AG6 VGA_IN_RED6 Y11 VGA_IN_RED7 W11 VGA_IN_GREEN0 Y8 VGA_IN_GREEN1 Y9 VGA_IN_GREEN...

Page 39: ...ML507 board These pins are not connected on the ML505 and ML506 boards Table 1 21 shows the CPU trace debug connections from P22 to the FPGA and BDM Figure 1 7 Combined Trace Debug Connector Pinout T...

Page 40: ..._23 A23 23 TRC_TS1O AF10 24 MICTOR_25 A21 25 TRC_TS2O AF9 26 MICTOR_27 A20 27 TRC_TS1E AK9 28 MICTOR_29 A19 29 TRC_TS2E AK8 30 MICTOR_31 A18 31 TRC_TS3 AJ11 32 MICTOR_33 A16 33 TRC_TS4 AK11 34 MICTOR_...

Page 41: ...C 440 processor JTAG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for attachment in the FPGA fabric making it po...

Page 42: ...ransceivers s for general purpose connectivity The SMAs are designed and laid out to provide high quality GTP GTX connections for speeds up to 3 125 Gb s Although the ML50x provides access to the GTP...

Page 43: ...Pin P21 Description PCIE_RX_N AF1 B15 Integrated Endpoint block receive pair PCIE_RX_P AE1 B14 PCIE_TX_N AE2 A17 Integrated Endpoint block transmit pair PCIE_TX_P AD2 A16 PCIE_CLK_N AF3 A14 Integrate...

Page 44: ...le cannot be used to connect a SATA host to a SATA device that is PC to hard disk It is only intended for host to host loopback connections 42 SFP Connector The board contains a small form factor plug...

Page 45: ...Low Module Present SFP RT SEL Jumper J81 Jumper Off Full Bandwidth Jumper On Reduced Bandwidth SFP LOS Test Point TP22 High Loss of Receiver Signal Low Normal Operation LED DS40 LED Off Loss of Receiv...

Page 46: ...frequencies for applications such as Gigabit Ethernet and SONET see Table 1 31 page 47 For other frequencies consult the ICS843001 21 data sheet for more information The 25 MHz oscillator is socketed...

Page 47: ...al oscillator This clock is sent to the GTPs driving the SGMII or onboard loopback interfaces Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode...

Page 48: ...signals specified in Table 1 33 For more information about soft touch connectors see www agilent com find softtouch Table 1 33 Landing Pad Signals on XGI Header Pad Number Header Pin FPGA Pin A1 HDR1_...

Page 49: ...stem Monitor User Guide Ref 14 Please note that the circuitry connected to the 16 AUX channels on the ML50x are connected in a non optimal fashion as they are implemented without anti alias filtering...

Page 50: ...ic channel sequencer allows a user defined selection of parameters to be automatically monitored and user programmable averaging is enabled to ensure robust noise free measurements The System Monitor...

Page 51: ...9 U32 J4 28 HDR2_28_SM_11_P VAUXN 10 T34 J4 22 HDR2_22_SM_10_N VAUXP 10 U33 J4 24 HDR2_24_SM_10_P VAUXN 11 R32 J4 18 HDR2_18_DIFF_2_N VAUXP 11 R33 J4 20 HDR2_20_DIFF_2_P VAUXN 12 R34 J4 14 HDR2_14_DI...

Page 52: ...ignals Table 1 35 describes the IIC devices attached to each of the four buses Table 1 35 IIC Bus Connections IIC FPGA Pins Device Bus Name Address SCL SDA EEPROM IC Main 0x50 F9 F8 Fan Controller IC...

Page 53: ...LD The PC4 JTAG connection to the JTAG chain allows a host computer to download bitstreams to the FPGA using the iMPACT software tool PC4 also allows debug tools such as the ChipScope Pro Analyzer or...

Page 54: ...select which of the four modes to use for programming the FPGA The configuration mode DIP switches on the board must be set to match the programming method being used by the Platform Flash PROM When...

Page 55: ...RocketIO GTP transceivers 1 XC5VLX50T 1CES 1FFG1136 Rev A 0483688 01 0483688 02 ML506 XC5VSX50T 1C 1FFG1136 Rev A 0483729 03 and up ML506 is an SXT platform that supports RocketIO GTP transceivers 1...

Page 56: ...56 www xilinx com ML505 ML506 ML507 Evaluation Platform UG347 v3 1 1 October 7 2009 R Downloaded from Elcodis com electronic components distributor...

Page 57: ...equipment Xilinx download cable JTAG flying wires Downloading to the ML50x Board 1 Connect a Xilinx download cable to the board using flying leads connected to jumper J3 Figure B 1 2 Click Start iMPA...

Page 58: ...ogramming the chip cycle the power by turning off the board power switch 8 After turning the board back on verify that the clock frequencies are correct Figure B 2 Programming the IDT5V9885 on the ML5...

Page 59: ...Guide for PCI Express Designs 12 UG193 XtremeDSP Design Considerations 13 UG191 Virtex 5 FPGA Configuration User Guide 14 UG192 Virtex 5 FPGA System Monitor User Guide 15 UG195 Virtex 5 FPGA Packaging...

Page 60: ...009 R The Xilinx ChipScope Pro Tool Web page offers the following material supporting the ChipScope Pro Analyzer 24 UG029 ChipScope Pro Software and Cores User Guide 25 UG213 ChipScope Pro Serial I O...

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