Xilinx M401, User Manual, Page: 31 / 32

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 31
UG080 (v2.5) May 24, 2006
Configuration Options
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Configuration Options
The FPGA on the ML40 x evaluation platform can be configured by four major devices:
•
Parallel Cable IV cable (JTAG)
•
System ACE controller (JTAG)
•
Platform Flash memory
•
Linear flash + CPLD
The following section provides an overview of the possible ways the board can be
configured.
JTAG (Parallel Cable IV Cable and System ACE Controller)
The FPGA, Platform Flash memory, and CPLD can be configured through the JTAG port.
The JTAG chain of the board is illustrated in
Figure 5 .
The chain starts at the PC4 connector and goes through the System ACE controller, the
Platform Flash memory, the FPGA, the CPLD, and an optional extension of the chain to the
expansion card. Jumper J26 determines if the JTAG chain should be extended to the
expansion card.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug. The JTAG chain is also used to program the Platform Flash memory and
the CPLD.
The PC4 JTAG connection to the JTAG chain allows a host PC to download bitstreams to
the FPGA using the iMPACT software tool. PC4 also allows debug tools such as the
ChipScope™ Pro Analyzer or a software debugger to access the FPGA.
The System ACE controller can also program the FPGA through the JTAG port. Using an
inserted CompactFlash card or Microdrive storage device, configuration information can
be stored and played out to the FPGA. The System ACE controller supports up to eight
configuration images that can selected using the three configuration address DIP switches.
Under FPGA control, the System ACE chip can be instructed to reconfigure to any of the
eight configuration images.
The configuration source selector switch should be in the SYS ACE setting if the use of the
System ACE controller is desired.
When set correctly, the System ACE controller programs the FPGA upon power-up if a
CompactFlash card is present or whenever a CompactFlash card is inserted. Pressing the
System ACE reset button also causes the System ACE controller to program the FPGA if a
CompactFlash card is present.
Figure 5: JTAG Chain
UG080_05_090804
PlatFlash FPGA SysACE
TSTTDI TDI
TSTDO
CFGTDO TDO
CFGTDI
PC4
TDI TDO
CPLD
TDI TDO
Expansion
TDI
TDO
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