Xilinx M401, User Manual, Page: 17 / 32

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 17
UG080 (v2.5) May 24, 2006
Detailed Description
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4. Oscillator Sockets
The ML40 x evaluation platform has two crystal oscillator sockets, each wired for standard
LVTTL-type oscillators. (A 100-MHz oscillator is pre-installed in the X1 SYSCLK socket.)
These connect to the FPGA clock pins as shown in
Table 4 . The oscillator sockets accept
half-sized oscillators and are powered by the 3.3V supply.
5. LCD Brightness and Contrast Adjustment
Turning potentiometer R1 adjusts the image contrast of the character LCD.
6. DIP Switches (Active-High)
Eight general purpose (active-High) DIP switches are connected to the user I/O pins of the
FPGA.
Table 5 summarizes these connections.
Note:
On the ML403 board, these DIP switches are not installed.
Table 4: Oscillator Socket Connections
Label Clock Name FPGA Pin
X1 SYSCLK AE14
X6 USERCLK AD12
Table 5: DIP Switches Connections (SW1)
SW1 FPGA Pin
1 R20
2 R19
3 T26
4 U26
5 U23
6 V23
7 U25
8 U24
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