Xilinx M401, User Manual, Page: 19 / 32

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 19
UG080 (v2.5) May 24, 2006
Detailed Description
R
8. User Push Buttons (Active-High)
Five active-High user push buttons are available for general purpose usage and are
arranged in a North-East-South-West-Center orientation (only the
center one is cited in
Figure 2, page 12 ). Table 7 summarizes the user push button connections.
9. CPU Reset Button (Active-Low)
The CPU reset button is an active-Low push button intended to be used as a system or user
reset button. This button is wired only to an FPGA I/O pin, so it can also be used as a
general purpose button (see
Table 8 ).
Table 7: User Push Button Connections
Reference
Designator
Label/Definition FPGA Pin
SW3 GPIO Switch North E7
SW5 GPIO Switch East F10
SW4 GPIO Switch South A6
SW7 GPIO Switch West E9
SW6 GPIO Switch Center B6
Table 8: CPU Reset Connections
Reference
Designator
Label/Definition FPGA Pin
SW10 FPGA CPU RESET D6
www.BDTIC.com/XILINX